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 11.4.6.1.1 PRE (Preamble)
The preamble (pre) consists of 32 contiguous logic 1 bits on MII_MDIO with 32 corresponding cycles on MII_MDC to provide the PHY with a pattern that it can use to establish synchronization. The preamble is optional as determined by NOPRE. 11.4.6.1.2 ST (Start of Frame)
The start of frame (st) is indicated by a <01> pattern. This pattern ensures transitions from the default logic 1 line state to 0 and then returns to 1. 11.4.6.1.3 OP (Operation Code)
The operation code (op) for a read instruction is <10>. For a write operation, the operation code is <01>. 11.4.6.1.4 PHYAD (PHY Address)
The PHY address (phyad) is a 5-bit field, allowing up to 32 unique PHY addresses. The first address bit transmitted is the MSB of the address. 11.4.6.1.5 REGAD (Register Address)
The register address (regad) is a 5-bit field, allowing 32 individual registers to be addresses within each PHY. The first register bit transmitted is the MSB of the address. 11.4.6.1.6 TA (Turnaround)
The turnaround (ta) field is a two bit time spacing between the register address field and the data field of an MII management frame to avoid contention on the MII_MDIO signal during a read operation. For a read transaction, both the MAC and the PHY remain in a high impedance state for the first bit time of the turnaround. The PHY drives a 0 bit during the second bit time of the turnaround of a read transaction. During a write transaction, the MAC drives a 1 bit for the first bit time of the turnaround and a 0 bit for the second bit time of the turnaround. 11.4.6.1.7 DATA (Data)
The data (data) field is 16 bits wide. The first data bit transmitted and received is the MSB of the data. 11.4.6.1.8 IDLE (IDLE Condition)
During idle condition (idle), MII_MDIO is in the high impedance state.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 343
Chapter 11 Ethernet Media Access Controller (EMACV1)
11.4.6.2 Read Operation
To perform a read operation through MII management, the OP field in MCMST must be written to 10 while the BUSY bit is clear. The PADDR field in MPADR indicates which PHY device is addressed and the RADDR in MRADR indicates which 16-bit register is read from the PHY device. The MII management creates an MII management frame and serially shifts it out to the PHY through the MII_MDIO pin. After the turnaround field, the PHY serially shifts the register data from the PHY to the EMAC through the MII_MDIO pin. After the read MII management frame operation has completed, the BUSY bit clears, the MRDATA register is updated, and the MMCIF bit in IEVENT is set. If not masked (MMCIE in IMASK is set), an MII management transfer complete interrupt is pending while this flag is set.
MDC
MDIO
(MAC)
z z z
MDIO
(PHY)
32 1s 0 1 1 0 0 1 1 1 0 0 0 0 0 1 z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 z
Optional Preamble Start Opcode (Read) PHY Address (PHYAD = 0Eh) Register Address TA (REGAD = 01h) Register Data Idle
Figure 11-26. Typical MDC/MDIO Read Operation
11.4.6.3 Write Operation
To perform a write operation through MII management, the OP field in MCMST must be written to 01 while the BUSY bit is clear. The PADDR field in MPADR indicates which PHY device is addressed and the RADDR bit in MRADR indicates which 16-bit register is read from the PHY device. The MII management creates an MII management frame and serially shifts it out to the PHY through the MII_MDIO pin. After the turnaround field, the MWDATA register is serially shifted to the PHY through the MII_MDIO pin. After the write MII management frame operation has completed, the BUSY bit is cleared and the MMCIF bit in IEVENT is set. If not masked (MMCIE in IMASK is set), an MII management transfer complete interrupt is pending while this flag is set.
MDC MDIO
(MAC)
z
32 1s 0 1 0 1 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 z
Optional Start Opcode Preamble (Write) PHY Address (PHYAD = 0Eh) Register Address (REGAD = 01h) TA Register Data Idle
Figure 11-27. Typical MDC/MDIO Write Operation
11.4.7
Loopback
The MII transmit data stream is internally looped back as an MII receive data stream if the MLB bit is set. The MII_TXCLK and MII_RXCLK are internally driven from the system clock. MII_RXD is driven from MII_TXD. MII_RXDV is driven from MII_TXEN. MII_RXER is driven from MII_TXER. The
MC9S12NE64 Data Sheet, Rev. 1.1 344 Freescale Semiconductor
Functional Description
MII_COL, MII_CRS, MII_MDC, and MII_MDIO signals are disabled. During loopback, the MII to external and internal PHYs are disabled. Loopback mode requires that the user set the FDX bit to configure for full-duplex mode. Loopback connects the outs to the ins and relies on the unidirectional nature of full duplex to transfer data in parallel. The bidirectional nature of half duplex does not allow the RX to accept transmit data without using some kind of intermediate storage buffer.
11.4.8
Software Reset
The EMAC provides a software reset capability. When the MACRST bit is set, all registers are reset to their default values. The EMACE bit is cleared. The receiver and transmitter are initialized. Any reception and/or transmission currently in progress is abruptly aborted.
11.4.9
Interrupts
When an interrupt event occurs, a bit is set in the IEVENT register. Note that bits in the IEVENT register are set by the event and remain set until cleared by software. If a bit in the IEVENT register is set and the corresponding bit is set in the IMASK register, the corresponding interrupt signal asserts. Individual interrupts are cleared by software by writing a 1 to the corresponding bit in the IEVENT register. The interrupt sources are listed in Table 11-12.
Table 11-12. Interrupt Vectors
Interrupt Source Receive Flow Control (RFCIF) Babbling Receive Error (BREIF) Receive Error (RXEIF) Receive Buffer A Overrun (RXAOIF) Receive Buffer B Overrun (RXBOIF) Receive Buffer A Complete (RXACIF) Receive Buffer B Complete (RXBCIF) MII Management Transfer Complete (MMCIF) Late Collision (LCIF) Excessive Collision (ECIF) Frame Transmission Complete (TXCIF) CCR Mask I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit I bit Local Enable IMASK (RFCIE) IMASK (BREIE) IMASK (RXEIE) IMASK (RXAOIE) IMASK (RXBOIE) IMASK (RXACIE) IMASK (RXBCIE) IMASK (MMCIE) IMASK (LCIE) IMASK (ECIE) IMASK (TXCIE)
11.4.10 Debug and Stop
During system debug (freeze) mode, the EMAC functions normally.When the system enters low-power stop mode, the EMAC is immediately disabled. Any receive in progress is dropped and any PAUSE timeout is cleared. The user must not enter low-power stop mode while TXACT or BUSY is set.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 345
Chapter 11 Ethernet Media Access Controller (EMACV1)
MC9S12NE64 Data Sheet, Rev. 1.1 346 Freescale Semiconductor
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.1 Introduction
The Ethernet physical transceiver (EPHY) is an IEEE 802.3 compliant 10BASE-T/100BASE-TX Ethernet PHY transceiver. The EPHY module supports both the medium-independent interface (MII) and the MII management interface. The EPHY requires a 25-MHz crystal for its basic operation.
12.1.1
* * *
Features
* * * * * * * * * * * * * * *
IEEE 802.3 compliant Full-/half-duplex support in all modes Medium-independent interface (MII), which has these characteristics: -- Capable of supporting both 10 Mbps and 100 Mbps data rates -- Data and delimiters are synchronous to clock references -- Provides independent four-bit wide transmit and receive data paths -- Provides a simple management interface Supports auto-negotiation Auto-negotiation next page ability Single RJ45 connection 1:1 common transformer Baseline wander correction Digital adaptive equalization Integrated wave-shaping circuitry Far-end fault detect MDC rates up to 25 MHz Supports MDIO preamble suppression Jumbo packet 2.5 V CMOS 2.5 V MII interface 125 MHz clock generator and timing recovery Loopback modes
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 347
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.1.2
.
Block Diagram
PHY_TXP PHY_TXN
PHY_RXP PHY_RXN
MII_RXCLK MII_RXDV MII_RXD[3:0] MII_RXER
PHY_RBIAS
PHY SUB BLOCK
MII_TXCLK MII_TXEN MII_TXD[3:0] MII_TXER MII_CRS MII_COL
MII_MDC
MII_MDIO MII INTERFACE IP BUS REGISTERS IP BUS SIGNALS
REF CLOCK
Figure 12-1. Ethernet Physical Transceiver (EPHY) Block Diagram
MC9S12NE64 Data Sheet, Rev. 1.1 348 Freescale Semiconductor
External Signal Descriptions
RXP 10BASE-T RECEIVER POLARITY CORRECTION SQUELCH LINK DETECT CLOCK RECOVERY MANCHESTER DECODE
RXN
MII AUTO NEGOTIATE COLLISION CARRIER SENSE
100BASE-TX LOOPBACK TXP 10BASE-T DRIVER 100BASE-TX DIG LOOP B 10BASE-T DIG LOOP B
TXN
MANCHESTER ENCODER DIGITAL WAVE SHAPING
MII LOOPBACK 100BASE-TX DRIVER SCRAMBLER MLT-3 ENCODE 4B / 5B ENCODE
RBIAS VOLTAGE/ CURRENT REFERENCES
10BASE-T PLL 100BASE-TX PLL
MANAGEMENT (MII) CONFIGURATION REGISTERS
Figure 12-2. PHY Sub Block Diagram
12.2
External Signal Descriptions
This section contains the EPHY external pin descriptions.
12.2.1
PHY_TXP -- EPHY Twisted Pair Output +
Ethernet twisted-pair output pin. This pin is high-impedance out of reset.
12.2.2
PHY_TXN -- EPHY Twisted Pair Output -
Ethernet twisted-pair output pin. This pin is high-impedance out of reset.
12.2.3
PHY_RXP -- EPHY Twisted Pair Input +
Ethernet twisted-pair input pin. This pin is high-impedance out of reset.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 349
MII CONNECTIONS REF CLOCK MDIO
100BASE-TX RECEIVER
VGA CONTROL (COARSE EQUALIZER) DIGITAL EQUALIZER SLICER TIMING CONTROL BLW CONTROL
MLT-3 DECODE DESCRAMBLER
4B/5B DECODE
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.2.4
PHY_RXN -- EPHY Twisted Pair Input -
Ethernet twisted-pair input pin. This pin is high-impedance out of reset.
12.2.5
PHY_RBIAS -- EPHY Bias Control Resistor
Connect a 1.0% external resistor, RBIAS (see Electrical Characteristics chapter), between the PHY_RBIAS pin and analog ground. Place this resistor as near to the chip pin as possible. Stray capacitance must be kept to less than 10 pF (>50 pF will cause instability). No high-speed signals are permitted in the region of RBIAS.
12.2.6
PHY_VDDRX, PHY_VSSRX -- Power Supply Pins for EPHY Receiver
Power is supplied to the EPHY receiver through PHY_VDDRX and PHY_VSSRX. This 2.5 V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VDDR is tied to ground.
12.2.7
PHY_VDDTX, PHY_VSSTX -- Power Supply Pins for EPHY Transmitter
External power is supplied to the EPHY transmitter through PHY_VDDTX and PHY_VSSTX. This 2.5 V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VDDR is tied to ground.
12.2.8
PHY_VDDA, PHY_VSSA -- Power Supply Pins for EPHY Analog
Power is supplied to the EPHY PLLs through PHY_VDDA and PHY_VSSA. This 2.5 V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VDDR is tied to ground.
12.2.9
COLLED -- Collision LED
Flashes in half-duplex mode when a collision occurs on the network if EPHYCTL0 LEDEN bit is set.
12.2.10 DUPLED -- Duplex LED
Indicates the duplex of the link, which can be full-duplex or half-duplex if EPHYCTL0 LEDEN bit is set.
12.2.11 SPDLED -- Speed LED
Indicates the speed of a link, which can be 10 Mbps or 100 Mbps if EPHYCTL0 LEDEN bit is set.
12.2.12 LNKLED -- Link LED
Indicates whether a link is established with another network device if EPHYCTL0 LEDEN bit is set.
MC9S12NE64 Data Sheet, Rev. 1.1 350 Freescale Semiconductor
Memory Map and Register Descriptions
12.2.13 ACTLEC -- Activity LED
Flashes when data is received by the device if EPHYCTL0 LEDEN bit is set.
12.3
Memory Map and Register Descriptions
This section provides a detailed description of all registers accessible in the EPHY.
12.3.1
Module Memory Map
Table 12-1 gives an overview of all registers in the EPHY memory map. The EPHY occupies 48 bytes in the memory space. The register address results from the addition of base address and address offset. The base address is determined at the MCU level. The address offset is defined at the module level.
Table 12-1. EPHY Module Memory Map
Address Offset $__00 $__01 $__02 $__03 Use Ethernet Physical Transceiver Control Register 0 (EPHYCTL0) Ethernet Physical Transceiver Control Register 1 (EPHYCTL1) Ethernet Physical Transceiver Status Register (EPHYSR) RESERVED Access R/W R/W R/W R
12.3.2
Register Descriptions
12.3.2.1 Ethernet Physical Transceiver Control Register 0 (EPHYCTL0)
Module Base + $0
7 R EPHYEN W RESET: 0 6 ANDIS 1 5 DIS100 1 4 DIS10 1 3 LEDEN 0 2 EPHYWAI 0 1 0 0 0 EPHYIEN 0
= Unimplemented or Reserved
Figure 12-3. Ethernet Physical Transceiver Control Register 0 (EPHYCTL0)
Read: Anytime Write: See each bit description EPHYEN -- EPHY Enable This bit can be written anytime. 1 = Enables EPHY 0 = Disables EPHY
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 351
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
ANDIS -- Auto Negotiation Disable This bit can be written anytime, but the value is latched in the ANE bit of the MII PHY control register (MII address 0.12) only when the EPHYEN bit transitions from 0 to 1. 1 = Auto negotiation is disabled after start-up. A 0 is latched in the ANE bit of the MII PHY control register (MII address 0.12), and upon completion of the start-up delay (tStart-up), the EPHY will bypass auto-negotiation. The mode of operation will be determined by the manual setting of MII registers. 0 = Auto negotiation is enabled after start-up. A 1 is latched in the ANE bit of the MII PHY control register (MII address 0.12), and upon completion of the start-up delay (tStart-up), the EPHY will enter auto-negotiation. The mode of operation will be automatically determined. DIS100 -- Disable 100 BASE-TX PLL This bit can be written anytime. Allows user to power down the clock generation PLL for 100BASE-TX clocks. 1 = Disables 100BASE-TX PLL 0 = 100BASE-TX PLL state determined by EPHY operation mode DIS10 -- Disable 10BASE-T PLL This bit can be written anytime. Allows user to power down the clock generation PLL for 10BASE-T clocks. 1 = Disables 10BASE-T PLL 0 = 10 BASE-T PLL state determined by EPHY operation mode LEDEN -- LED Drive Enable This bit can be written anytime. 1 = Enables the EPHY to drive LED signals. 0 = Disables the EPHY to drive LED signals. EPHYWAI -- EPHY Module Stops While in Wait This bit can be written anytime. 1 = Disables the EPHY module while the MCU is in wait mode. EPHY interrupts cannot be used to bring the MCU out of wait. 0 = Allows the EPHY module to continue running during wait. EPHYIEN -- EPHY Interrupt Enable This bit can be written anytime. 1 = Enables EPHY module interrupts 0 = Disables EPHY module interrupts
12.3.2.2 Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)
Module Base + $1
R W RESET: 7 0 0 6 0 0 5 0 0 4 3 2 1 0 PHYADD4 PHYADD3 PHYADD2 PHYADD1 PHYADD0 0 0 0 0 0
= Unimplemented or Reserved
Figure 12-4. Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)
MC9S12NE64 Data Sheet, Rev. 1.1 352 Freescale Semiconductor
Memory Map and Register Descriptions
Read: Anytime Write: See each bit description PHYADD[4:0] -- EPHY Address for MII Requests These bits can be written anytime, but the EPHY address is latched to the MII PHY address register (MII address 21.4:0) only when the EPHYEN bit transitions from 0 to 1. PHYADD4 is the MSB of the of the EPHY address.
12.3.2.3 Ethernet Physical Transceiver Status Register (EPHYSR)
Module Base + $2
R W RESET: 7 0 0 6 0 0 5 100DIS 1 4 10DIS 1 3 0 0 2 0 0 1 0 0 0 EPHYIF 0
= Unimplemented or Reserved
Figure 12-5. Ethernet Physical Transceiver Status Register (EPHYSR)
Read: Anytime Write: See bit descriptions 100DIS -- EPHY Port 100BASE-TX mode status This bit is not writable -- read only. Output to indicate EPHY port Base100-TX mode status. 1 = EPHY port 100BASE-TX disabled 0 = EPHY port 100BASE-TX enabled 10DIS -- EPHY Port 10BASE-T mode status This bit is not writable. Output to indicate EPHY port 10BASE-T mode status. 1 = EPHY port 10BASE-T disabled 0 = EPHY port 10BASE-T enabled EPHYIF -- EPHY Interrupt Flag EPHYIF indicates that interrupt conditions have occurred. To clear the interrupt flag, write a 1 to this bit after reading the interrupt control register via the MII management interface. 1 = EPHY interrupt has occurred 0 = EPHY interrupt has not occurred
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 353
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.3.3
MII Registers
Table 12-2 gives an overview of all registers in the EPHY that are accessible via the MII management interface. These registers are not part of the MCU memory map.
Table 12-2. MII Registers
Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 %00000 %00001 %00010 %00011 %00100 %00101 %00110 %00111 %01000 %01001 %01010 %01011 %01100 %01101 %01110 %01111 %10000 %10001 %10010 Use Control Register Status Register PHY Identification Register 1 PHY Identification Register 2 Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Transmit RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Interrupt Control Register Proprietary Status Register Proprietary Control Register Access Read/Write Read/Write4 Read/Write4 Read/Write4 Read/Write Read/Write4 Read/Write4 Read/Write Read/Write1 Read/Write1 Read/Write1 Read/Write1 Read/Write1 Read/Write1 Read/Write1 Read/Write1 Read/Write Read/Write4 Read/Write
1. Always read $00 2. Writable only in special modes (test_mode = 1) 4. Write has no effect.
NOTE Bit notation for MII registers is: Bit 20.15 refers to MII register address 20 and bit number 15.
12.3.3.1 EPHY Control Register
MII Register Address 0 (%00000)
15 R W RESET:
RESET
14
LOOP BACK
13
DATA RATE
12
ANE
11
PDWN
10
ISOL
9
RAN
8
DPLX
7
COL TEST
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0 1 X 0 0 = Unimplemented or Reserved
0
1
0
0
0
0
0
0
0
0
Figure 12-6. Control Register
Read: Anytime Write: Anytime
MC9S12NE64 Data Sheet, Rev. 1.1 354 Freescale Semiconductor
Memory Map and Register Descriptions
RESET -- EPHY Reset Resetting a port is accomplished by setting this bit to 1. 1 = The PHY will reset the port's status and registers to the default values. The PHY will also reset the PHY to its initial state. After the reset is complete, the PHY clears this bit automatically. The reset process will be completed within 1.3 ms of this bit being set. While the preamble is suppressed, the management interface must not receive an ST within three MDC clock cycles following a software reset. 0 = No effect LOOPBACK -- Digital Loopback Mode Determines Digital Loopback Mode 1 = Enables digital loopback mode. Port will be placed in loopback mode. Loopback mode will allow the TXD data to be sent to the RXD data circuitry within 512 bit times. The PHY will be isolated from the medium (no transmit or receive to the medium allowed) and the MII_COL signal will remain de-asserted, unless this bit is set. 0 = Disables digital loopback mode DATARATE -- Speed Selection The link speed will be selected either through the auto-negotiation process or by manual speed selection. ANE allows manual speed selection while it is set to 0. While auto-negotiation is enabled, DATARATE can be read or written but its value is not required to reflect speed of the link. 1 = While auto-negotiation is disabled, selects 100 Mbps operation 0 = While auto-negotiation is disabled, selects 10 Mbps operation ANE -- Auto-Negotiation Enable The ANE bit determines whether the A/N process is enabled. When auto-negotiation is disabled, DATARATE and DPLX determine the link configuration. While auto-negotiation is enabled, bits DATARATE and DPLX do not affect the link. 1 = Enables auto-negotiation 0 = Disables auto-negotiation PDWN -- Power Down When this bit is set, the port is placed in a low power consumption mode. 1 = Port is placed in a low power consumption mode. Normal operation will be allowed within 0.5 s after PDWN and ISOL are changed to 0. During a transition to power-down mode (or if already in power down mode), the port will respond only to management function requests through the MI interface. All other port operations will be disabled. When power-down mode is exited, all register values are maintained. The port will start its operation based on the register values. 0 = Normal operation ISOL -- Isolate 1 = Isolates the port's data path signals from the MII. The port will not respond to changes on MII_TXDx, MII_TXEN, and MII_TXER inputs, and it will present high impedance on MII_TXCLK, MII_RXCLK, MII_RXDV, MII_RXER, MII_RXDx, MII_COL, and MII_CRS outputs. The port will respond to management transactions while in isolate mode. 0 = Normal operation
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 355
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
RAN -- Restart Auto-Negotiation The RAN bit determines when the A/N process can start processing. 1 = When auto-negotiation is enabled (ANE=1), the auto-negotiation process will be restarted. After auto-negotiation indicates that it has been initialized, this bit is cleared. When bit ANE is cleared to indicate auto-negotiation is disabled, RAN must also be 0. 0 = Normal operation. DPLX -- Duplex Mode This mode can be selected by either the auto-negotiation process or manual duplex selection. Manual duplex selection is allowed only while the auto-negotiation process is disabled (ANE=0). While the auto-negotiation process is enabled (ANE = 1), the state of DPLX has no effect on the link configuration. While loopback mode is asserted (LOOPBACK =1), the value of DPLX will have no effect on the PHY. 1 = Indicates full-duplex mode 0 = Indicates half-duplex mode COLTEST -- Collision Test The collision test function will be enabled only if the loopback mode of operation is also selected (LOOPBACK = 1). 1 = Forces the PHY to assert the MII_COL signal within 512 bit times from the assertion of MII_TXEN and de-assert MII_COL within 4 bit times of MII_TXEN being de-asserted. 0 = Normal operation
12.3.3.2 Status Register
This register advertises the capabilities of the port to the MII.
MII Register Address 1 (%00001)
15 R W RESET:
100 T4
14
100X FD
13
100X HD
12
10T FD
11
10T HD
10
0
9
0
8
0
7
0
6
SUP PRE
5
AN COMP
4
REM FLT
3
AN ABL
2
LNK STST
1
JAB DT
0
EX CAP
0
1
1
1
1
0
0
0
0
1
0
0
1
0
0
1
= Unimplemented or Reserved
Figure 12-7. Status Register
Read: Anytime Write: Writes have no effect 100T4 --100BASE-T4 1 = Indicates PHY supports 100BASE-T4 transmission 0 = Indicates the PHY does not support 100BASE-T4 transmission This function is not implemented in the EPHY module. 100XFD --100BASE-TX Full-Duplex 1 = Indicates PHY supports 100BASE-TX full-duplex mode 0 = Indicates PHY does not support 100BASE-TX full-duplex mode
MC9S12NE64 Data Sheet, Rev. 1.1 356 Freescale Semiconductor
Memory Map and Register Descriptions
100XHD --100BASE-TX Half-Duplex 1 = Indicates the PHY supports 100BASE-TX half-duplex mode 0 = Indicates the PHY does not support 100BASE-TX half-duplex mode 10TFD --10BASE-T Full-Duplex 1 = Indicates the PHY supports 10BASE-T full-duplex mode 0 = Indicates the PHY does not support 10BASE-T full-duplex mode 10THD --10BASE-T Half-Duplex 1 = Indicates the PHY supports 10BASE-T half-duplex mode 0 = Indicates the PHY does not support 10BASE-T half-duplex mode SUPPRE --MF Preamble Suppression 1 = Indicates that management frames are not required to contain the preamble stream 0 = Indicates that management frames are required to contain the preamble stream ANCOMP --Auto-Negotiation Complete To inform the management interface (MI) that it has completed processing, ANCOMP is set by the A/N process. After it has been started, the auto-negotiation process uses link code words to exchange capability information and establish the highest common denominator (HCD) for link transactions. 1 = Indicates that the auto-negotiation process has completed and that the contents of registers 4 through 7 are valid. 0 = Indicates that the auto-negotiation process has not completed and that the contents of registers 4 through 7 are not valid REMFLT -- Remote Fault Possible remote faults (RF) a) The link partner transmits the RF bit (5.13=1) b) Link partner protocol is not 00001 (5.4:0) c) Link partner advertises only T4 capability (5.9:5) d) No common operation mode found between PHY and the link partner. After it is set, REMFLT is cleared each time register 1 is read via the management interface. REMFLT is also cleared by a PHY reset. 1 = Indicates that a remote fault condition has been detected. 0 = No fault detected ANABL -- Auto-Negotiation Ability 1 = Indicates that PHY has auto-negotiation ability 0 = Indicates that PHY does not have auto-negotiation ability LNKSTST -- Link Status The PHY sets this bit when it determines that a valid link has been established. The occurrence of a link failure will cause LNKSTST to be cleared. After it has been cleared, it remains cleared until it is read via the management interface. 1 = Indicates a valid link has been established 0 = Indicates a valid link has NOT been established
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 357
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
JABDT --Jabber Detect After it is set, JABDT is cleared each time register 1 is read via the management interface. JABDT is also cleared by a PHY reset. For 100BASE-TX operation, this signal will always be cleared. 1 = Indicates that a jabber condition has been detected 0 = Indicates that no jabber condition has been detected EXCAP -- Extended capability 1 = Indicates that the extended register set (registers 2-31) has been implemented in the PHY. 0 = Indicates that the extended register set (registers 2-31) has NOT been implemented in the PHY
12.3.3.3 EPHY Identifier Register 1
Registers $_02 and $_03 provide the PHY identification code.
MII Register Address 2 (%00010)
15 R W RESET: 14 13 12 11 10 9 8
PHYID
7
6
5
4
3
2
1
0
0
0
0
0
01
0
0
0
0
0
1
0
1
1
0
0
= Unimplemented or Reserved
Figure 12-8. EPHY Identifier Register 1
Read: Anytime Write: Writes have no effect -- Read only PHYID -- PHY ID Number Composed of bits 3:18 of the organization unique identifier (OUI).
12.3.3.4 EPHY Identifier Register 2
Registers $_02 and $_03 provide the PHY identification code.
MII Register Address 3 (%00011)
15 R W RESET: 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PHYID MODELNUMBER REVISIONNUMBER
0
0 0 0 0 0 = Unimplemented or Reserved
0
0
0
0
0
1
0
0
0
1
Figure 12-9. EPHY Identifier Register 2
Read: Anytime Write: Writes have no effect -- Read only PHYID -- PHY ID number organization unique identifier. Composed of bits 15:10. MODELNUMBER -- Manufacturers model number. Composed of bits 9:4. REVISIONNUMBER -- Manufacturers revision number. Composed of bits 3:0.
MC9S12NE64 Data Sheet, Rev. 1.1 358 Freescale Semiconductor
Memory Map and Register Descriptions
12.3.3.5 Auto-Negotiate (A/N) Advertisement Register
The auto-negotiation (A/N) process requires four registers to communicate link information with its link partner: A/N advertisement register (MII register 4), A/N link partner ability register (MII register 5), A/N expansion register (MII register 6), and the A/N next page transmit register (MII register 7). Figure 12-10 shows the contents of the A/N advertisement register. On power-up, before A/N starts, the register sets the selector field, bits 4.4:0, to 00001 to indicate that it is IEEE Standard 802.3 compliant. The technology ability fields (4.9:5) are set according to the values in the MII status register (1.15:11). The MI can set the technology ability field bits before renegotiations to allow management to auto-negotiate to an alternate common mode.
MII Register Address 4 (%00100)
15 R W RESET:
NXTP
14
0
13
RFLT
12
0
11
0
10
FLCTL
9
0
8
TAF 100FD
7
TAF 100HD
6
TAF 10FD
5
TAF 10HD
4
3
2
1
0
SELECTORFIELD[4:0]
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
= Unimplemented or Reserved
Figure 12-10. Auto Negotiate Advertisement Register
Read: Anytime Write: Never NXTP -- Next Page 1 = Capable of sending next pages 0 = Not capable of sending next pages RFLT -- Remote Fault 1 = Remote fault 0 = No remote fault FLCTL -- Flow Control 1 = Advertise implementation of the optional MAC control sublayer and pause function as specified in IEEE standard clause 31 and anex 31B of 802.3. Setting FLCTL has no effect except to set the corresponding bit in the FLP stream 0 = No MAC-based flow control TAF100FD -- 100BASE-TX Full-Duplex 1 = 100BASE-TX full -duplex capable 0 = Not 100BASE-TX full-duplex capable TAF100HD -- 100BASE-TX Half-Duplex 1 = 100BASE-TX half-duplex capable 0 = Not 100BASE-TX half-duplex capable TAF10FD -- 10BASE-T Full-Duplex 1 = 10BASE-T full-duplex capable 0 = Not 10BASE-T full-duplex capable
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 359
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
TAF10HD -- 10BASE-T Half-Duplex 1 = 10BASE-T half-duplex capable 0 = Not 10BASE-T half-duplex capable
12.3.3.6 Auto Negotiation Link Partner Ability (Base Page)
Figure 12-11 shows the contents of the A/N link partner ability register. The register can only be read by the MI and will be written by the auto-negotiation process when it receives a link code word advertising the capabilities of the link partner. This register has a dual purpose: exchange of base page information as shown in Figure 12-11, and exchange of next page information as shown in Figure 12-12.
MII Register Address 5 (%00101) (Base Page)
15 R W RESET:
NXTP
14
ACK
13
RFLT
12
11
10
FCTL
9
TAF 100T4
8
TAF 100FD
7
TAF 100HD
6
TAF 10FD
5
TAF 10HD
4
3
2
1
0
TAF[1:0]
SELECTORFIELD[4:0]
X
X X X X X = Unimplemented or Reserved
X
X
X
X
X
X
X
X
X
X
Figure 12-11. Auto Negotiation Link Partner Ability Register (Base Page)
Read: Write: NXTP -- Next Page 1 = Link partner capable of sending next pages 0 = Link partner not capable of sending next pages ACK -- Acknowledge 1 = Link Partner has received link code word 0 = Link Partner has not received link code word RFLT -- Remote Fault 1 = Remote fault 0 = No remote fault FLCTL -- Flow Control 1 = Advertises implementation of the optional MAC control sublayer and pause function as specified in IEEE standard clause 31 and anex 31B of 802.3. Setting FLCTL has no effect on the PHY. 0 = No MAC-based flow control TAF100T4 -- 100BASE-T4 Full-Duplex 1 = Link partner is 100BASE-T4 capable 0 = Link partner is not 100BASE-T4 capable This function is not implemented in the EPHY. TAF100FD -- 100BASE-TX Full-Duplex 1 = Link partner is 100BASE-TX full-duplex capable 0 = Link partner is not 100BASE-TX full-duplex capable
MC9S12NE64 Data Sheet, Rev. 1.1 360 Freescale Semiconductor
Memory Map and Register Descriptions
TAF100HD -- 100BASE-TX Half-Duplex 1 = Link partner is 100BASE-TX half-duplex capable 0 = Link partner is not 100BASE-TX half-duplex capable TAF10FD -- 10BASE-T Full-Duplex 1 = Link partner is10BASE-T full-duplex capable 0 = Link partner is not 10BASE-T full-duplex capable TAF10HD -- 10BASE-T Half-Duplex 1 = Link partner is 10BASE-T half-duplex capable 0 = Link partner is not 10BASE-T half-duplex capable
12.3.3.7 Auto Negotiation Link Partner Ability (Next Page)
MII Register Address 5 (%00101) (Next Page)
15 R W RESET:
NXTP
14
ACK
13
MSGP
12
ACK2
11
TGL
10
9
8
7
6
5
4
3
2
1
0
Message/Unformatted Code Field [10:0]
X
X X X X X = Unimplemented or Reserved
X
X
X
X
X
X
X
X
X
X
Figure 12-12. Auto Negotiation Link Partner Ability Register (Next Page)
Read: Anytime Write: See each field description NXTP -- Next Page 1 = Additional next pages will follow 0 = Last page transmitted ACK -- Acknowledge ACK is used to acknowledge receipt of information. 1 = Link partner has received link code word 0 = Link partner has not received link code word MSGP -- Message Page 1 = Message page 0 = Unformatted page ACK2 -- Acknowledge 2 ACK2 is used to indicate that the receiver is able to act on the information (or perform the task) defined in the message. 1 = Receiver is able to perform the task defined in the message 0 = Receiver is unable to perform the task defined in the message TGL -- Toggle 1 = Previous value of the transmitted link code word equalled 0 0 = Previous value of the transmitted link code word equalled 1
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 361
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
Message/Unformatted Code Field Message code field -- Predefined code fields defined in IEEE 802.3u-1995 Annex 28C Unformatted code filed -- 11-bit field containing an arbitrary value
12.3.3.8 Auto-Negotiation Expansion Register
Figure 12-13 shows the contents of the A/N expansion register. The MI process can only read this register. This register contains information about the A/N capabilities of the port's link partner and information on the status of the parallel detection mechanism.
MII Register Address 6 (%00110)
15 R W RESET:
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
3
2
1
0
PDFLT LPNPA NXTPA PRCVD LPANA
0
0 0 0 0 0 = Unimplemented or Reserved
0
0
0
0
0
0
0
1
0
0
Figure 12-13. Auto-Negotiation Expansion Register
Read: Anytime Write: Never PDFLT -- Parallel Detection Fault This bit is used to indicate that zero or more than one of the NLP receive link integrity test function for 100BASE-TX have indicated that the link is ready (link_status=READY) when the A/N wait timer has expired. PDFLT will be reset to 0 after a read of register 6. 1 = Parallel detection fault has occurred 0 = Parallel detection fault has not occurred LPNPA -- Link Partner Next Page Able Bit to indicate whether the link partner has the capability of using NP. 1 = Link partner is next page able 0 = Link partner is not next page able NXTPA -- Next Page Able This bit is used to inform the MI and the link partner whether the port has next page capabilities. 1 = The port has next page capabilities 0 = The port does not have next page capabilities PRCVD -- Page Received Bit is used to indicate whether a new link code word has been received and stored in the A/N link partner ability register (MII register 5). PRCVD is reset to 0 after register 6 is read. 1 = Three identical and consecutive link code words have been received from link partner 0 = Three identical and consecutive link code words have not been received from link partner
MC9S12NE64 Data Sheet, Rev. 1.1 362 Freescale Semiconductor
Memory Map and Register Descriptions
LPANA -- Link Partner A/N Able Indicates whether the link partner has A/N capabilities. 1 = Link partner is A/N able 0 = Link partner is not A/N able
12.3.3.9 Auto Negotiation Next Page Transmit
Figure 12-14 shows the contents of the A/N next page transmit register. The MI writes to this register if it needs to exchange more information with the link partner. The PHY defaults to sending only a NULL message page to the link partner unless the STA overrides the values in the register. Next pages will be transmitted until the link partner has no more pages to transmit and bit 7.15 has been cleared by the STA.
MII Register Address 7 (%00111)
15 R W RESET:
NXTP
14
0
13
MSGP
12
ACK2
11
TGL
10
9
8
7
6
5
4
3
2
1
0
Message/Unformatted Code Field [10:0]
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
= Unimplemented or Reserved
Figure 12-14. Auto Negotiation Next Page Transmit Register
Read: Anytime Write: Never NXTP -- Next Page 1 = Additional next pages will follow 0 = Last page to transmit MSGP -- Message Page 1 = Message page 0 = Unformatted page ACK2 -- Acknowledge 2 ACK2 is used to indicate that the receiver is able to act on the information (or perform the task) defined in the message. 1 = Receiver is able to perform the task defined in the message 0 = Receiver is unable to perform the task defined in the message TGL -- Toggle 1 = Previous value of the transmitted link code word equalled 0 0 = Previous value of the transmitted link code word equalled 1 Message/Unformatted Code Field Message code field -- Predefined code fields defined in IEEE 802.3u-1995 Annex 28C Unformatted code field -- Eleven bit field containing an arbitrary value
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 363
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
12.3.4
PHY-Specific Registers
PHY also contains a number of registers to set its internal mode of operation. These registers can be set through the external management interface to determine capabilities such as speed, test-mode, circuit bypass mode, interrupt setting, etc. The PHY register set includes registers 16 through 29. These registers are not part of the MCU memory map.
12.3.4.1 Interrupt Control Register
MII Register Address 16 (%10000)
15 R W RESET:
0
14
ACKIE
13
PRIE
12
LCIE
11
ANIE
10
PDFIE
9
RFIE
8
JABIE
7
0
6
ACKR
5
PGR
4
LKC
3
ANC
2
PDF
1
RMTF
0
JABI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-15. Interrupt Control Register
Read: Anytime Write: Anytime ACKIE -- Acknowledge Bit Received Interrupt Enable 1 = Enable interrupt when the acknowledge bit is received from the link partner 0 = Disable interrupt when acknowledge bit is received PRIE -- Page Received INT Enable 1 = Enable interrupt when a new page is received 0 = Disable interrupt when a page is received LCIE -- Link Changed Enable 1 = Enable interrupt when the link status changes 0 = Disable interrupt when the link status changes ANIE -- Auto-Negotiation Changed Enable 1 = Enable interrupt when the state of the auto-negotiation state machine has changed since the last access of this register 0 = Disable interrupt when the state of the auto-negotiation state machine has changed since the last access of this register PDFIE -- Parallel Detect Fault Enable 1 = Enable interrupt on a parallel detect fault 0 = Disable interrupt on a parallel detect fault RFIE -- Remote Fault Interrupt Enable 1 = Enable interrupt on a parallel detect fault 0 = Disable interrupt on a parallel detect fault JABIE -- Jabber Interrupt Enable 1 = Enable setting interrupt on detection of a jabber condition 0 = Disable setting interrupt on detection of a jabber condition
MC9S12NE64 Data Sheet, Rev. 1.1 364 Freescale Semiconductor
Memory Map and Register Descriptions
ACKR -- Acknowledge Bit Received 1 = Acknowledge bit has been received from the link partner 0 = Acknowledge bit has not been received since the last access of this register. (ACK bit 14 of the auto-negotiation link partner ability register was set by receipt of link code word) PGR -- Page Received 1 = A new page has been received from the link partner 0 = A new page has not been received from the link partner since the last access of this register (Bit 1 was set by a page received event) LKC -- Link Changed 1 = The link status has changed since the last access of this register 0 = The link status has not changed since the last access of this register. (LNK bit 14 of the proprietary status register was changed) ANC -- Auto-Negotiation Changed 1 = The auto-negotiation status has changed since the last access of this register 0 = The auto-negotiation status has not changed since the last access of this register PDF -- Parallel Detect Fault 1 = A parallel-detect fault has occurred since the last access of this register 0 = A parallel-detect fault has not been detected since the last access of this register. (Bit 4 was set by rising edge of parallel detection fault) RMTF -- Remote Fault 1 = A remote fault condition has been detected since the last access of this register 0 = A remote fault condition has not been detected since the last access of this register. (RMTF bit 4 of the status register was set by rising edge of a remote fault) JABI -- Jabber Interrupt 1 = A jabber condition has been detected since the last access of this register 0 = A jabber condition has not been detected since the last access of this register (JABD bit 1 of the status register was set by rising edge of jabber condition)
12.3.4.2 Proprietary Status Register
MII Register Address 17 (%10001)
15 R W RESET:
0
14
LNK
13
DPMD
12
SPD
11
0
10
9
8
ANC MODE
7
0
6
0
5
PLR
4
0
3
0
2
0
1
0
0
0
ANNC PRCVD
0
1 1 1 0 0 = Unimplemented or Reserved
0
(1)
0
0
0
0
0
0
0
0
Figure 12-16. Proprietary Status Register
Read: Anytime Write:
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 365
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
LNK -- Link Status This is a duplicate of LNKSTAT bit 2 of the status register (1.2). 1 = Link is down 0 = Link is up DPMD -- Duplex Mode 1 = Full-duplex 0 = Half-duplex SPD -- Speed 1 = 100 Mbps 0 = 10 Mbps ANNC -- Auto-Negotiation Complete This is a duplicate of ANCOMP bit 5 of the status register (1.5) 1 = A-N complete 0 = A-N not complete PRCVD -- Page Received 1 = Three identical and consecutive link code words have been received 0 = Three identical and consecutive link code words have not been received ANCMODE -- Auto-Negotiation (A-N) Common Operating Mode This bit is only valid while the ANNC bit 10 is 1 1 = A common operation mode was not found 0 = A-N is complete and a common operation mode has been found PLR -- Polarity Reversed (10BASE-T) 1 = 10BASE-T receive polarity is reversed 0 = 10BASE-T receive polarity is normal
12.3.4.3 Proprietary Control Register
MII Register Address 18 (%10010)
R W RESET: 15 0 0 14
FE FLTD
13
MIILBD
12
0
11
1
10
JBDE
9
LNK TSTD
8
POL CORD
7
ALGD
6
ENC BYP
5
SCR BYP
4
TRD ANALB
3
TR TST
2
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-17. Proprietary Control Register
The miscellaneous (EMISC) register provides visibility of internal counters used by the EMAC. Read: Anytime Write: Anytime
MC9S12NE64 Data Sheet, Rev. 1.1 366 Freescale Semiconductor
Functional Description
FEFLTD -- Far End Fault Disable 1 = Far end fault detect is disabled 0 = Far end fault detect on receive and transmit is enabled. This applies only while auto-negotiation is disabled MIILBO -- MII Loopback Disable 1 = Disable MII loopback 0 = MII transmit data is looped back to the MII receive pins JBDE -- Jabber Detect Enable (10BASE-T) 1 = Enable jabber detection 0 = Disable jabber detection LNKTSTD -- Link Test Disable (10BASE-T) 1 = Disable 10BASE-T link integrity test 0 = 10BASE-T link integrity test enabled POLCORD -- Disable Polarity Correction (10BASE-T) 1 = 10BASE-T receive polarity correction is disabled 0 = 10BASE-T receive polarity is automatically corrected ALGD -- Disable Alignment 1 = Un-aligned mode. Available only in symbol mode 0 = Aligned mode ENCBYP -- Encoder Bypass 1 = Symbol mode and bypass 4B/5B encoder and decoder 0 = Normal mode SCRBYP -- Scrambler Bypass Mode (100BASE-TX) 1 = Bypass the scrambler and de-scrambler 0 = Normal TRDANALB -- Transmit and Receive Disconnect and Analog Loopback 1 = High-impedance twisted pair transmitter. Analog loopback mode overrides and forces this bit 0 = Normal operation TRTST -- Transmit and Receive Test (100BASE-TX) 1 = Transmit and receive data regardless of link status 0 = Normal operation
12.4
Functional Description
The EPHY is an IEEE 802.3 compliant 10/100 Ethernet physical transceiver. The EPHY can be configured to support 10BASE-T or 100BASE-TX applications. The EPHY is configurable via internal registers which are accessible through the MII management interface as well as limited configurability using the EPHY register map. There are five basic modes of operation for the EPHY: * Power down/initialization * Auto-negotiate
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 367
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
* * *
10BASE-T 100BASE-TX Low-power
12.4.1
Power Down/Initialization
Upon reset, the EPHYEN bit, in the Ethernet physical transceiver control register 0 (EPHYCTL0), is cleared and EPHY is in its lowest power consumption state. All analog circuits are powered down. The twisted-pair transmitter and receiver pins (PHY_TXP, PHY_TXN, PHY_RXP, and PHY_RXN) are high-impedance. The MII management interface is not accessible. All MII registers are initialized to their reset state. The ANDIS, DIS100, and DIS10 bits, in the EPHYCTL0 register, have no effect until the EPHYEN bit is set. The EPHYEN bit can be set or cleared by a register write at any time. Prior to enabling the EPHY, setting EPHYEN to 1, the MII PHY address PHYADD[4:0] must be set in the Ethernet physical transceiver control register 1 (EPHYCTL1), and the ANDIS, DIS100, DIS10 bits, in the EPHYCTL0 register, must be configured for the desired start-up operation. Whenever the EPHYEN bit transitions from 0 to 1, MDIO communications must be delayed until the completion of a start-up delay period (tStart-up, see Figure 12-19).
MC9S12NE64 Data Sheet, Rev. 1.1 368 Freescale Semiconductor
Functional Description
RESET or EPHYEN=0
Set PHYADD[4:0], and ANDIS, DIS100, DIS10
Set EPHYEN=1
PHYADD[4:0] and ANDIS become latched in MII registers
Delay for tStart-up
Configure MII registers via MDIO
Initialization Complete Figure 12-18. EPHY Start-Up / Initialization Sequence
EPHYEN
MDIO
tStart-up Figure 12-19. EPHY Start-Up Delay
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 369
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
If the auto-negotiation mode of operation is desired, the ANDIS bit in the EPHYCTL0 must be set to 0 and the DIS100 and DIS10 bits must be cleared prior to setting EPHYEN to 1. Refer to Section 12.4.2, "Auto-Negotiation," for more information on auto-negotiation operation. If the mode of operation will be set manually, the ANDIS bit must be set to 1 in the EPHYCTL0 register and the DIS100 and DIS10 bits must be cleared prior to setting EPHYEN to 1. After the EPHYEN bit has been set and the start-up delay period is completed, the mode of operation can be configured through the MII registers. Table 12-3 summarizes the MII register configuration and operational modes.
Table 12-3. Operational Configuration While Auto-Negotiation is Disabled1
Bit 0.12 Auto Neg. 0 0 0 0 0 0 Bit 0.13 Data Rate 0 0 1 1 1 1 Bit 0.8 Duplex 1 0 1 1 1 1 Bit 18.6 Encoder Bypass X X 0 1 1 1 Bit 18.5 Scrambler Bypass X X 0 0 0 1 Bit 18.7 Symbol Unalign X X 0 0 1 0 Operation 10BASE-T full-duplex 10BASE-T half-duplex 100BASE-TX full-duplex 100BASE-TX full-duplex with encoder bypass (symbol mode) -- aligned 100BASE-TX full-duplex with encoder bypass (symbol mode) -- unaligned 100BASE-TX full-duplex with scrambler and encoder bypassed (symbol mode), aligned 100BASE-TX full-duplex with scrambler and encoder bypassed (symbol mode), unaligned 100BASE-TX half-duplex
0
1
1
1
1
1
0
1
1
0
0
0
0
Symbol mode is not supported.
12.4.2
Auto-Negotiation
Auto-negotiation is used to determine the capabilities of the link partner. Auto-negotiation is compliant with IEEE 802.3 clause 28. In this case, the PHY will transmit fast link pulse (FLP) bursts to share its capabilities with the link partner. If the link partner is also capable of performing auto-negotiation, it will also send FLP bursts. The information shared through the FLP bursts will allow both link partners to find the highest common mode (if it exists). If no common mode is found, the remote fault bit (1.4) will be set. A remote fault is defined as a condition in which the PHY and the link partner cannot establish a common operating mode. Configuring auto-negotiation advertisement register sets the different auto-negotiation advertisement modes. If the link partner does not support auto-negotiation, it will transmit either normal link pulses (NLP) for 10 Mbps operation, or 100 Mbps idle symbols. Based on the received signal, the PHY determines whether the link partner is 10 Mbps capable or 100 Mbps capable. The ability to do this is called parallel detection. If using parallel detection, the link will be configured as a half-duplex link. After parallel detection has established the link configuration, the remote fault bit will be set if the operating mode does not match the pre-set operating modes.
MC9S12NE64 Data Sheet, Rev. 1.1 370 Freescale Semiconductor
Functional Description
Figure 12-20 shows the main blocks used in the auto-negotiation function. The transmit block allows transmission of fast link pulses to establish communications with partners that are auto-negotiation able. The receive block determines the capabilities of the link partner and writes to the link partner ability register (register 5). The arbitration block determines the highest common mode of operation to establish the link.
MR_ADV_ABILITY[15:0]
MR_PARALLEL_DETECTION_FAULT MR_AUTONEG_COMPLETE
MR_LP_ADV_ABILITY[15:0]
MR_ADV_ABILITY[3:0]
MR_LP_ADV_ABILITY[3:0]
complete_ack transmit_ability transmit_ack TRANSMIT transmit_disable flp_link_good ack_finished ARBITRATION
flp_receive_idle match_wo_ack match_w_ack receive_done flp_link_good RECEIVE
CLK POWER_ON MR_MAIN_RESET MR_AUTONEG_ENABLE
1 2
1 LP_LINK_CONTROL[1:0] 2 LP_LINK_STATUS[1:0]
NLP RECEIVE LINK INTEGRITY TEST
TD_AUTONEG
TX_LINK_CONTROL[1:0] TX_LINK_STATUS[1:0]
DO
RD
LINKPULSE
LINK_TEST_RECEIVE
Figure 12-20. Auto-Negotiation
12.4.3
10BASE-T
The 10BASE-T interface implements the physical layer specification for a 10 Mbps over two pairs of twisted-pair cables. The specifications are given in clause 14 of the IEEE 802.3 standard. In 10BASE-T mode, Manchester encoding is used. When transmitting, nibbles from the MII are converted to a serial bit stream and then Manchester encoded. When receiving, the Manchester encoded bit stream is decoded and converted to nibbles for presentation to the MII.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 371
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
A 2.5 MHz internal clock is used for nibble wide transactions. A 10 MHz internal clock is used for serial transactions.
TX MII PARALLEL TO SERIAL MANCHESTER ENCODER DIGITAL FILTER PHY_TXN PHY_TXP
CARRIER SENSE
JABBER
DIGITAL LOOPBACK (bit 0.14)
LINE TRANSMITTER/ LINE RECEIVER
RX MII
SERIAL TO PARALLEL
MANCHESTER DECODER AND TIMING RECOVERY
POLARITY CHECK
SQUELCH
PHY_RXN PHY_RXP
Figure 12-21. 10BASE-T Block Diagram
Parallel to Serial: Converts the 4-bit wide nibbles from the MII to serial format before the information is processed by subsequent blocks. Manchester Encoder: Allows encoding of both the clock and data in one bit stream. A logical one is encoded as a zero when the clock is high and a one when the clock is low. A logical zero is encoded as a one when the clock is high and a zero when the clock is low. Digital Filter: Performs pre-emphasis and low pass filtering of the input Manchester data. DAC: Converts the digital data to an analog format before transmission on the media. Carrier Sense: In half-duplex operation, carrier is asserted when either the transmit or receive medium is active. In full-duplex operation, carrier asserted only on reception of data. During receive, carrier sense is asserted during reception of a valid preamble, and de-asserted after reception of an EOF. Loopback: Enabled when bit 0.14 is asserted. This loopback mode allows for the Manchester encoded and filtered data to be looped back to the squelch block in the receive path. All the 10BASE-T digital functions are exercised during this mode. The transmit and receive channels are disconnected from the media. MII loopback (18.13) must be disabled to allow for correct operation of the digital loopback (0.14). Link Generator: Generates a 100 ns duration pulse at the end of every 12 ms period of the transmission path being idle (TXEN de-asserted). This pulse is used to keep the 10BASE-T link operational in the absence of data transmission.
MC9S12NE64 Data Sheet, Rev. 1.1 372 Freescale Semiconductor
Functional Description
Link Integrity Test: Used to determine whether the 10BASE-T link is operational. If neither data nor a link pulse is received for 64 ms, then the link is considered down. While the link is down, the transmit, loopback, collision detect, and SQE functions are disabled. The link down state is exited after receiving data or four link pulses. Jabber: Prevents the transmitter from erroneously transmitting for too long a period. The maximum time the device can transmit is 50,000 bit times. When the jabber timer is exceeded, the transmit output goes idle for 0.525 s. This function can be disabled with the jabber inhibit register bit (18.10). Squelch: Used to determine whether active data, a link pulse, or an idle condition exists on the 10BASE-T receive channel. While an idle or link pulse condition exists, a higher squelch level is used for greater noise immunity. The squelch output is used to determine when the Manchester decoder should operate. The output is also used to determine when an end of packet is received. Polarity Check: By examining the polarity of the received link pulses, EPHY can determine whether the received signal is inverted. If the pulses are inverted, this function changes the polarity of the signal.This feature is activated if eight inverted link pulses are received or four frames with inverted EOF are encountered. Manchester Decoder and Timing Recovery: Decodes the Manchester encoded data. The receive data and clock are recovered during this process. Serial to Parallel: Converts the serial bit stream from the Manchester decoder to the required MII parallel format. PMD Sublayer: Transmits and receives signals compliant with IEEE 802.3, Section 14. Line Transmitter and Line Receiver: These analog blocks allow the EPHY to drive and receive data from the 10BASE-T media.
12.4.4
100BASE-TX
100BASE-TX specifies operation over two pairs of category 5 unshielded twisted-pair cable (UTP). The EPHY implementation includes the physical coding sublayer (PCS), the physical medium attachment (PMA), and the physical medium dependent (PMD) sublayer. The block diagram for 100BASE-TX operation is shown in Figure 12-22.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 373
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
PCS TX 4B5B ENCODER PARALLEL TO SERIAL
PMA
PMD MLT3 ENCODER SLOPE CONTROL LINE DRIVER
SCRAMBLER
MII CARRIER SENSE PMA
DIGITAL ANALOG LOOPBACK LOOPBACK (bit 0.14) (bit 18.4)
LINK MONITOR
RX
4B5B DECODER
SERIAL TO PARALLEL AND SYMBOL ALIGNMENT
DESCRAMBLER
MLT3 DECODER
EQUALIZER AND TIMING RECOVERY
BASELINE WANDER
Figure 12-22. 100BASE-TX Block Diagram
12.4.4.1 Sublayers
12.4.4.1.1 PCS Sublayer
The PCS sublayer is the MII interface that provides a uniform interface to the reconciliation sublayer. The services provided by the PCS include: * Encoding/decoding of MII data nibbles to/from 5-bit code-groups (4B/5B) * Carrier sense and collision indications * Serialization/deserialization of code-groups for transmission/reception on the PMA * Mapping of transmit, receive, carrier sense, and collision detection between the MII and the underlying PMA Serial to Parallel and Symbol Alignment: This block looks for the occurrence of the JK symbol to align the serial bit stream and convert it to a parallel format. Carrier Sense: In full-duplex mode, carrier sense is only asserted while the receive channel is active. The carrier sense examines the received data bit stream looking for the SSD, the JK symbol pair. In the idle state, IDLE symbols (all logic ones) will be received. If the first 5-bit symbols received after an idle stream forms the J symbol (11000) it asserts the CRS signal. At this point the second symbol is checked to confirm the K symbol (10001). If successful, the following aligned data (symbols) are presented to the 4B/5B decoder. If the JK pair is not confirmed, the false carrier detect is asserted and the idle state is re-entered. Carrier sense is de-asserted when the ESD (end-of-stream) delimiter, the TR symbol pair, is found, or when an idle state is detected. In half-duplex, CRS is also asserted on transmit. Parallel to Serial: This block takes parallel data and converts it to serial format.
MC9S12NE64 Data Sheet, Rev. 1.1 374 Freescale Semiconductor
Functional Description
4B/5B Encoder/Decoder: The 4B/5B encoder converts the 4-bit nibbles from the reconciliation sublayer to a 5-bit code group. 12.4.4.1.2 PMA Sublayer
The PMA provides medium-independent means for the PCS and other bit-oriented clients (e.g., repeaters) to support the use of a range of physical media. For 100BASE-TX the PMA performs these functions: * Mapping of transmit and receive code-bits between the PMA's client and the underlying PMD * Generating a control signal indicating the availability of the PMD to a PCS or other client * Synchronization with the auto-negotiation function * Generating indications of carrier activity and carrier errors from the PMD * Recovery of clock from the NRZI data supplied by the PMD 12.4.4.1.3 PMD Sublayer
For 100BASE-TX, the ANSI X3.263: 199X (TP-PMD) standard is used. These signalling standards, called PMD sublayers, define 125 Mbps, full-duplex signalling systems that use STP and UTP wiring. Scrambler/De-scrambler: The scrambler and de-scrambler used in EPHY meet the ANSI Standard X3.263-1995 FDDI TP-PMD. The purpose of the scrambler is to randomize the 125 Mbps data on transmission resulting in a reduction of the peak amplitudes in the frequency spectrum. The de-scrambler restores the received 5-bit code groups to their unscrambled values. The scrambler input data (plaintext) is encoded by modulo 2 addition of a key stream to produce a ciphertext bit stream. The key stream is a periodic sequence of 2047 bits generated by the recursive linear function X[n] = X[n-11] + X[n-9] (modulo 2). If not transmitting data, the scrambler encodes and transmits idles. This allows a pattern to use by the de-scrambler to synchronize and decode the scrambled data. The implementation of the scrambler and de-scrambler is as shown in Appendix G of the ANSI Standard X3.263-1995. For test, the scrambler can be bypassed by setting bit 18.5. Scrambler bypass mode is a special type of interface for 100BASE-TX operation that bypasses the scrambler and de-scrambler operation. This mode is typically used for test so that input and output test vectors match. In this mode, idles are not sent and the MAC must provide idles. MLT-3 Encoder/Decoder: An MLT-3 encoder is used in the transmit path to convert NRZ bit stream data from the PMA sublayer into a three-level code. This encoding results in a reduction in the energy over the critical frequency range. The MLT-3 decoder converts the received three-level code back to an NRZ bit stream. Baseline Wander: The use of the scrambler and MLT-3 encoding can cause long run lengths of 0s and 1s that can produce a DC component. The DC component cannot be transmitted through the isolation transformers and results in baseline wander. Baseline wander reduces noise immunity because the base line moves nearer to either the positive or negative signal comparators. To correct for this EPHY uses DC
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 375
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
restoration to restore the lost DC component of the recovered digital data to correct the baseline wander problem. Timing Recovery: The timing recovery block locks onto the incoming data stream, extracts the embedded clock, and presents the data synchronized to the recovered clock. In the event that the receive path is unable to converge to the receive signal, it resets the MSE-good (bit 25.15) signal. The clock synthesizer provides a center frequency reference for operation of the clock recovery circuit in the absence of data. Adaptive Equalizer: At a data rate of 125 Mbps, the cable introduces significant distortion due to high frequency roll off and phase shift. The high frequency loss is mainly due to skin effect, which causes the conductor resistance to rise as the square of the frequency. The adaptive equalizer will compensate for signal amplitude and phase distortion incurred from transmitting with different cable lengths. Loopback: If asserted by bit 0.14, data encoded by the MLT3 encoder block is looped back to the MLT3 decoder block while the transmit and receive paths are disconnected from the media. A second loopback mode for 100BASE-TX is available by setting bit 18.13 (MII loopback) to a logical 1. This loopback mode takes the MII transmit data and loops it directly back to the MII receive pins. Again, the transmit and receive paths are disconnected from the media. MII loopback has precedence over the digital loopback if both are enabled at the same time. A third loopback mode is available by setting bit 18.4 high. This analog loopback mode takes the MLT3 encoded data and loops it back through the base line wander and analog receive circuits. Line Transmitter and Line Receiver: These analog blocks allow EPHY to drive and receive data to/from the 100BASE-TX media. The transmitter is designed to drive a 100- UTP cable. Link Monitor: The link monitor process is responsible for determining whether the underlying receive channel is providing reliable data. If a failure is found, normal operation will be disabled. As specified in the IEEE 802.3 standard, the link is operating reliably if a signal is detected for a period of 330 s. Far End Fault: While the auto-negotiation function is disabled, this function is used to exchange fault information between the PHY and the link partner.
12.4.5
Low Power Modes
There are several reduced power configurations available for the EPHY.
12.4.5.1 Stop Mode
If the MCU executes a STOP instruction, the EPHY will be powered down and all internal MII registers reset to their default state. Upon exiting stop mode, the EPHY will exit the power-down state and latch the values previously written to the EPHYCTL0 and EPHYCTL1 registers. The MII registers will have to be re-initialized after the start-up delay (tStart-up) has expired.
MC9S12NE64 Data Sheet, Rev. 1.1 376 Freescale Semiconductor
Functional Description
12.4.5.2 Wait Mode
If the MCU executes a WAIT instruction with the EPHYWAI bit set, the EPHY will be powered down and all internal MII registers reset to their default state. Upon exiting STOP mode the EPHY will exit the power-down state and latch the values previously written to the EPHYCTL0 and EPHYCTL1 registers. The MII registers must be re-initialized after the start-up delay (tStart-up) has expired.
12.4.5.3 MII Power Down
This mode disconnects the PHY from the network interface (three-state receiver and driver pins). Setting bit 0.11 of the port enters this mode. In this mode, the management interface is accessible but all internal chip functions are in a zero power state. In this mode all analog blocks except the PLL clock generator and band gap reference are in low power mode. All digital blocks except the MDIO interface and management registers are inactive.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 377
Chapter 12 Ethernet Physical Transceiver (EPHYV2)
MC9S12NE64 Data Sheet, Rev. 1.1 378 Freescale Semiconductor
Chapter 13 Penta Output Voltage Regulator (VREGPHYV1) 13.1 Introduction
13.1.1 Overview
Block VREG_PHY is a penta output voltage regulator providing five separate 2.5V (typ) supplies differing in the amount of current that can be sourced. The regulator input voltage is 3.3V+/-10% .
13.1.2 Features
The block VREG_PHY includes these distinctive features: * * * Five parallel, linear voltage regulators -- Bandgap reference Power On Reset (POR) Low Voltage Reset (LVR)
13.1.3 Modes of Operation
There are three modes VREG_PHY can operate in: * Full Performance Mode (FPM) (CPU is not in Stop Mode) The regulator is active, providing the nominal supply voltage of 2.5V with full current sourcing capability at all outputs. Features LVR (Low Voltage Reset) and POR (Power-On Reset) are available. Reduced Power Mode (RPM) (CPU is in Stop Mode) The purpose is to reduce power consumption of the device. The output voltage may degrade to a lower value than in Full Performance Mode, additionally the current sourcing capability is substantially reduced. Only the POR is available in this mode, LVR are disabled. Shutdown Mode Controlled by VREGEN (see device level specification for connectivity of VREGEN). This mode is characterized by minimum power consumption. The regulator outputs are in a high impedance state, only the POR feature is available, LVR is disabled. This mode must be used to disable the chip internal regulator VREG_PHY, i.e. to bypass the VREG_PHY to use external supplies.
*
*
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 379
Chapter 13 Penta Output Voltage Regulator (VREGPHYV1)
13.1.4 Block Diagram
Figure 13-1 shows the function principle of VREG_PHY by means of a block diagram. The regulator core REG consists of file parallel subblocks, providing five independent output voltages.
Figure 13-1. VREG_PHY - Block Diagram
VDDRAUX3 VDDRAUX2 VDDRAUX1
REG5 REG4 REG3
VDDAUX3 VSSAUX3 VDDAUX2 VSSAUX2 VDDAUX1 VSSAUX1
VDDPLL VDDR VDDA VSSA REG
REG2
VSSPLL
VDD
REG1
LVR
LVR
POR
POR
VSS
VREGEN
CTRL LVI
REG: Regulator Core CTRL: Regulator Control LVR: Low Voltage Reset POR: Power-on Reset PIN
MC9S12NE64 Data Sheet, Rev. 1.1 380 Freescale Semiconductor
Signal Description
13.2 Signal Description
13.2.1 Overview
Due to the nature of VREG_PHY being a voltage regulator providing the chip internal power supply voltages most signals are power supply signals connected to pads. Table 13-1 shows all signals of VREG_PHY associated with pins.
Table 13-1. VREG_PHY - Signal Properties
Name VDDR VDDRAUX1 VDDRAUX2 VDDRAUX3 VDDA VSSA VDD VSS VDDPLL VSSPLL VDDAUX1 VSSAUX1 VDDAUX2 VSSAUX2 VDDAUX3 VSSAUX3 VREGEN (optional) Port -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Function VREG_PHY power input (positive supply) VREG_PHY power input (positive supply) VREG_PHY power input (positive supply) VREG_PHY power input (positive supply) VREG_PHY quiet input (positive supply) VREG_PHY quiet input (ground) VREG_PHY primary output (positive supply) VREG_PHY primary output (ground) VREG_PHY secondary output (positive supply) VREG_PHY secondary output (ground) VREG_PHY third output (positive supply) VREG_PHY third output (ground) VREG_PHY fourth output (positive supply) VREG_PHY fourth output (ground) VREG_PHY fifth output (positive supply) VREG_PHY fifth output (ground) VREG_PHY (Optional) Regulator Enable Reset State -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Pull up -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
13.2.2 Detailed Signal Descriptions
Check device level specification for connectivity of the signals.
13.2.2.1 VDDR,VDDRAUX1,2,3, VSS - Regulator Power Inputs
Signal VDDR/VDDRAUX1,2,3 are the power inputs of VREG_PHY. All currents sourced into the regulator loads flow through these pins. A chip external decoupling capacitor (100nF...220nF, X7R ceramic) between VDDR/VDDRAUX1,2,3 and VSS can smoothen ripple on VDDR/VDDRAUX1,2,3. If the regulator shall be bypassed, VDDR should be tied to ground. In Shutdown Mode pin VDDR should also be tied to ground on devices without VREGEN pin.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 381
Chapter 13 Penta Output Voltage Regulator (VREGPHYV1)
13.2.2.2 VDDA, VSSA - Regulator Reference Supply
Signals VDDA/VSSA which are supposed to be relatively quiet are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling capacitor (100nF...220nF, X7R ceramic) between VDDA and VSSA can further improve the quality of this supply.
13.2.2.3 VDD, VSS - Regulator Output1 (Core Logic)
Signals VDD/VSS are the primary outputs of VREG_PHY that provide the power supply for the core logic. These signals are connected to device pins to allow external decoupling capacitors (100nF...220nF, X7R ceramic). In Shutdown Mode an external supply at VDD/VSS can replace the voltage regulator.
13.2.2.4 VDDPLL, VSSPLL - Regulator Output2 (PLL)
Signals VDDPLL/VSSPLL are the secondary outputs of VREG_PHY that provide the power supply for the PLL and Oscillator. These signals are connected to device pins to allow external decoupling capacitors (100nF...220nF, X7R ceramic). In Shutdown Mode an external supply at VDDPLL/VSSPLL can replace the voltage regulator.
13.2.2.5 VDDAUX1,2,3, VSSAUX1,2,3 - Regulator Output3,4,5
Signals VDDAUX1,2,3/VSSAUX1,2,3 are the auxilliary outputs of VREG_PHY. These signals are connected to device pins to allow external decoupling capacitors (100nF...220nF, X7R ceramic). In Shutdown Mode an external supply at VDDAUX1,2,3/VSSAUX1,2,3 can replace the voltage regulator.
13.2.2.6 VREGEN - Optional Regulator Enable
This optional signal is used to shutdown VREG_PHY. In that case VDD/VSS and VDDPLL/VSSPLL must be provided externally. Shutdown Mode is entered with VREGEN being low. If VREGEN is high, the VREG_PHY is either in Full Performance Mode or in Reduced Power Mode. For the connectivity of VREGEN see device specification. NOTE Switching from FPM or RPM to shutdown of VREG_PHY and vice versa is not supported while MCU is powered.
MC9S12NE64 Data Sheet, Rev. 1.1 382 Freescale Semiconductor
Memory Map and Registers
13.3 Memory Map and Registers
13.3.1 Overview
VREG_PHY does not contain any CPU accessible registers.
13.4 Functional Description
13.4.1 General
Block VREG_PHY is a voltage regulator as depicted in Figure 13-1. The regulator functional elements are the regulator core (REG), a power-on reset module (POR) and a low voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the interface to the digital core logic but also handles the operating modes of VREG_PHY.
13.4.2 REG - Regulator Core
VREG_PHY, respectively its regulator core has five parallel, independent regulation loops (REG1 to REG5) that differ only in the amount of current that can be sourced to the connected loads. Therefore only REG1, providing the supply at VDD/VSS, is explained. The principle is also valid for REG2 to REG5. The regulator is a linear series regulator with a bandgap reference in its Full Performance Mode and a voltage clamp in Reduced Power Mode. All load currents flow from input VDDR or VDDRAUX1,2,3 to VSS or VSSPLL or VSSAUX1,2,3, the reference circuits are connected to VDDA and VSSA.
13.4.2.1 Full Performance Mode
In Full Performance Mode a fraction of the output voltage (VDD) and the bandgap reference voltage are fed to an operational amplifier. The amplified input voltage difference controls the gate of an output driver which basically is a large NMOS transistor connected to the output.
13.4.2.2 Reduced Power Mode
In Reduced Power Mode the driver gate is connected to a buffered fraction of the input voltage(VDDR). The operational amplifier and the bandgap are disabled to reduce power consumption.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 383
Chapter 13 Penta Output Voltage Regulator (VREGPHYV1)
13.4.3 POR - Power-On Reset
This functional block monitors output VDD. If VDD is below VPORD, signal POR is high, if it exceeds VPORD, the signal goes low. The transition to low forces the CPU in the power-on sequence. Due to its role during chip power-up this module must be active in all operating modes of VREG_PHY.
13.4.4 LVR - Low Voltage Reset
Block LVR monitors the primary output voltage VDD. If it drops below the assertion level (VLVRA) signal LVR asserts and when rising above the deassertion level (VLVRD) signal LVR negates again. The LVR function is available only in Full Performance Mode.
13.4.5 CTRL - Regulator Control
This part contains the register block of VREG_PHY and further digital functionality needed to control the operating modes. CTRL also represents the interface to the digital core logic.
13.5 Resets
13.5.1 General
This section describes how VREG_PHY controls the reset of the MCU.The reset values of registers and signals are provided in Section 13.3, "Memory Map and Registers." Possible reset sources are listed in Table 13-2.
Table 13-2. VREG_PHY - Reset Sources
Reset Source Power-on Reset Low Voltage Reset Local Enable always active available only in Full Performance Mode
13.5.2 Description of Reset Operation
13.5.2.1 Power-On Reset
During chip power-up the digital core may not work if its supply voltage VDD is below the POR deassertion level (VPORD). Therefore signal POR which forces the other blocks of the device into reset is kept high until VDD exceeds VPORD. Then POR becomes low and the reset generator of the device continues the start-up sequence. The power-on reset is active in all operation modes of VREG_PHY.
MC9S12NE64 Data Sheet, Rev. 1.1 384 Freescale Semiconductor
Interrupts
13.5.2.2 Low Voltage Reset
For details on low voltage reset see section Section 13.4.4, "LVR - Low Voltage Reset."
13.6 Interrupts
13.6.1 General
VREG_PHY does not generate any interrupts.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 385
Chapter 13 Penta Output Voltage Regulator (VREGPHYV1)
MC9S12NE64 Data Sheet, Rev. 1.1 386 Freescale Semiconductor
Chapter 14 Interrupt (INTV1)
14.1 Introduction
This section describes the functionality of the interrupt (INT) sub-block of the S12 core platform. A block diagram of the interrupt sub-block is shown in Figure 14-1.
INT
WRITE DATA BUS
HPRIO (OPTIONAL)
HIGHEST PRIORITY I-INTERRUPT
INTERRUPTS XMASK IMASK INTERRUPT INPUT REGISTERS AND CONTROL REGISTERS READ DATA BUS
WAKEUP HPRIO VECTOR
QUALIFIED INTERRUPTS
INTERRUPT PENDING RESET FLAGS VECTOR REQUEST PRIORITY DECODER VECTOR ADDRESS
Figure 14-1. INTV1 Block Diagram
The interrupt sub-block decodes the priority of all system exception requests and provides the applicable vector for processing the exception. The INT supports I-bit maskable and X-bit maskable interrupts, a non-maskable unimplemented opcode trap, a non-maskable software interrupt (SWI) or background debug
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 387
Chapter 14 Interrupt (INTV1)
mode request, and three system reset vector requests. All interrupt related exception requests are managed by the interrupt sub-block (INT).
14.1.1
Features
The INT includes these features: * Provides two to 122 I-bit maskable interrupt vectors (0xFF00-0xFFF2) * Provides one X-bit maskable interrupt vector (0xFFF4) * Provides a non-maskable software interrupt (SWI) or background debug mode request vector (0xFFF6) * Provides a non-maskable unimplemented opcode trap (TRAP) vector (0xFFF8) * Provides three system reset vectors (0xFFFA-0xFFFE) (reset, CMR, and COP) * Determines the appropriate vector and drives it onto the address bus at the appropriate time * Signals the CPU that interrupts are pending * Provides control registers which allow testing of interrupts * Provides additional input signals which prevents requests for servicing I and X interrupts * Wakes the system from stop or wait mode when an appropriate interrupt occurs or whenever XIRQ is active, even if XIRQ is masked * Provides asynchronous path for all I and X interrupts, (0xFF00-0xFFF4) * (Optional) selects and stores the highest priority I interrupt based on the value written into the HPRIO register
14.1.2
Modes of Operation
The functionality of the INT sub-block in various modes of operation is discussed in the subsections that follow. * Normal operation The INT operates the same in all normal modes of operation. * Special operation Interrupts may be tested in special modes through the use of the interrupt test registers. * Emulation modes The INT operates the same in emulation modes as in normal modes. * Low power modes See Section 14.4.1, "Low-Power Modes," for details
14.2
External Signal Description
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and XIRQ pin data.
MC9S12NE64 Data Sheet, Rev. 1.1 388 Freescale Semiconductor
Memory Map and Register Definition
14.3
Memory Map and Register Definition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
14.3.1
Module Memory Map
Table 14-1. INT Memory Map
Address Offset 0x0015 0x0016 0x001F Use Interrupt Test Control Register (ITCR) Interrupt Test Registers (ITEST) Highest Priority Interrupt (Optional) (HPRIO) Access R/W R/W R/W
14.3.2
14.3.2.1
Register Descriptions
Interrupt Test Control Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0 WRTINT ADR3 1 ADR2 1 ADR1 1 ADR0 1
0
0
0
0
= Unimplemented or Reserved
Figure 14-2. Interrupt Test Control Register (ITCR)
Read: See individual bit descriptions Write: See individual bit descriptions
Table 14-2. ITCR Field Descriptions
Field 4 WRTINT Description Write to the Interrupt Test Registers Read: anytime Write: only in special modes and with I-bit mask and X-bit mask set. 0 Disables writes to the test registers; reads of the test registers will return the state of the interrupt inputs. 1 Disconnect the interrupt inputs from the priority decoder and use the values written into the ITEST registers instead. Note: Any interrupts which are pending at the time that WRTINT is set will remain until they are overwritten. Test Register Select Bits Read: anytime Write: anytime These bits determine which test register is selected on a read or write. The hexadecimal value written here will be the same as the upper nibble of the lower byte of the vector selects. That is, an "F" written into ADR[3:0] will select vectors 0xFFFE-0xFFF0 while a "7" written to ADR[3:0] will select vectors 0xFF7E-0xFF70.
3:0 ADR[3:0]
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 389
Chapter 14 Interrupt (INTV1)
14.3.2.2
Interrupt Test Registers
7 6 5 4 3 2 1 0
R INTE W Reset 0 0 0 0 0 0 0 0 INTC INTA INT8 INT6 INT4 INT2 INT0
= Unimplemented or Reserved
Figure 14-3. Interrupt TEST Registers (ITEST)
Read: Only in special modes. Reads will return either the state of the interrupt inputs of the interrupt sub-block (WRTINT = 0) or the values written into the TEST registers (WRTINT = 1). Reads will always return 0s in normal modes. Write: Only in special modes and with WRTINT = 1 and CCR I mask = 1.
Table 14-3. ITEST Field Descriptions
Field 7:0 INT[E:0] Description Interrupt TEST Bits -- These registers are used in special modes for testing the interrupt logic and priority independent of the system configuration. Each bit is used to force a specific interrupt vector by writing it to a logic 1 state. Bits are named INTE through INT0 to indicate vectors 0xFFxE through 0xFFx0. These bits can be written only in special modes and only with the WRTINT bit set (logic 1) in the interrupt test control register (ITCR). In addition, I interrupts must be masked using the I bit in the CCR. In this state, the interrupt input lines to the interrupt sub-block will be disconnected and interrupt requests will be generated only by this register. These bits can also be read in special modes to view that an interrupt requested by a system block (such as a peripheral block) has reached the INT module. There is a test register implemented for every eight interrupts in the overall system. All of the test registers share the same address and are individually selected using the value stored in the ADR[3:0] bits of the interrupt test control register (ITCR). Note: When ADR[3:0] have the value of 0x000F, only bits 2:0 in the ITEST register will be accessible. That is, vectors higher than 0xFFF4 cannot be tested using the test registers and bits 7:3 will always read as a logic 0. If ADR[3:0] point to an unimplemented test register, writes will have no effect and reads will always return a logic 0 value.
14.3.2.3
Highest Priority I Interrupt (Optional)
7 6 5 4 3 2 1 0
R PSEL7 W Reset 1 1 1 1 0 0 1 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
0
= Unimplemented or Reserved
Figure 14-4. Highest Priority I Interrupt Register (HPRIO)
Read: Anytime Write: Only if I mask in CCR = 1
MC9S12NE64 Data Sheet, Rev. 1.1 390 Freescale Semiconductor
Functional Description
Table 14-4. HPRIO Field Descriptions
Field 7:1 PSEL[7:1] Description Highest Priority I Interrupt Select Bits -- The state of these bits determines which I-bit maskable interrupt will be promoted to highest priority (of the I-bit maskable interrupts). To promote an interrupt, the user writes the least significant byte of the associated interrupt vector address to this register. If an unimplemented vector address or a non I-bit masked vector address (value higher than 0x00F2) is written, IRQ (0xFFF2) will be the default highest priority interrupt.
14.4
Functional Description
The interrupt sub-block processes all exception requests made by the CPU. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below.
14.4.1
Low-Power Modes
The INT does not contain any user-controlled options for reducing power consumption. The operation of the INT in low-power modes is discussed in the following subsections.
14.4.1.1
Operation in Run Mode
The INT does not contain any options for reducing power in run mode.
14.4.1.2
Operation in Wait Mode
Clocks to the INT can be shut off during system wait mode and the asynchronous interrupt path will be used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
14.4.1.3
Operation in Stop Mode
Clocks to the INT can be shut off during system stop mode and the asynchronous interrupt path will be used to generate the wake-up signal upon recognition of a valid interrupt or any XIRQ request.
14.5
Resets
The INT supports three system reset exception request types: normal system reset or power-on-reset request, crystal monitor reset request, and COP watchdog reset request. The type of reset exception request must be decoded by the system and the proper request made to the core. The INT will then provide the service routine address for the type of reset requested.
14.6
Interrupts
As shown in the block diagram in Figure 14-1, the INT contains a register block to provide interrupt status and control, an optional highest priority I interrupt (HPRIO) block, and a priority decoder to evaluate whether pending interrupts are valid and assess their priority.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 391
Chapter 14 Interrupt (INTV1)
14.6.1
Interrupt Registers
The INT registers are accessible only in special modes of operation and function as described in Section 14.3.2.1, "Interrupt Test Control Register," and Section 14.3.2.2, "Interrupt Test Registers," previously.
14.6.2
Highest Priority I-Bit Maskable Interrupt
When the optional HPRIO block is implemented, the user is allowed to promote a single I-bit maskable interrupt to be the highest priority I interrupt. The HPRIO evaluates all interrupt exception requests and passes the HPRIO vector to the priority decoder if the highest priority I interrupt is active. RTI replaces the promoted interrupt source.
14.6.3
Interrupt Priority Decoder
The priority decoder evaluates all interrupts pending and determines their validity and priority. When the CPU requests an interrupt vector, the decoder will provide the vector for the highest priority interrupt request. Because the vector is not supplied until the CPU requests it, it is possible that a higher priority interrupt request could override the original exception that caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this exception instead of the original request. NOTE Care must be taken to ensure that all exception requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not be processed. If for any reason the interrupt source is unknown (e.g., an interrupt request becomes inactive after the interrupt has been recognized but prior to the vector request), the vector address will default to that of the last valid interrupt that existed during the particular interrupt sequence. If the CPU requests an interrupt vector when there has never been a pending interrupt request, the INT will provide the software interrupt (SWI) vector address.
14.7
Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request by the CPU is shown in Table 14-5.
Table 14-5. Exception Vector Map and Priority
Vector Address 0xFFFE-0xFFFF 0xFFFC-0xFFFD 0xFFFA-0xFFFB 0xFFF8-0xFFF9 0xFFF6-0xFFF7 0xFFF4-0xFFF5 System reset Crystal monitor reset COP reset Unimplemented opcode trap Software interrupt instruction (SWI) or BDM vector request XIRQ signal Source
MC9S12NE64 Data Sheet, Rev. 1.1 392 Freescale Semiconductor
Exception Priority
Table 14-5. Exception Vector Map and Priority
Vector Address 0xFFF2-0xFFF3 0xFFF0-0xFF00 IRQ signal Device-specific I-bit maskable interrupt sources (priority in descending order) Source
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 393
Chapter 14 Interrupt (INTV1)
MC9S12NE64 Data Sheet, Rev. 1.1 394 Freescale Semiconductor
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.1 Introduction
This section describes the functionality of the multiplexed external bus interface (MEBI) sub-block of the S12 core platform. The functionality of the module is closely coupled with the S12 CPU and the memory map controller (MMC) sub-blocks. Figure 15-1 is a block diagram of the MEBI. In Figure 15-1, the signals on the right hand side represent pins that are accessible externally. On some chips, these may not all be bonded out. The MEBI sub-block of the core serves to provide access and/or visibility to internal core data manipulation operations including timing reference information at the external boundary of the core and/or system. Depending upon the system operating mode and the state of bits within the control registers of the MEBI, the internal 16-bit read and write data operations will be represented in 8-bit or 16-bit accesses externally. Using control information from other blocks within the system, the MEBI will determine the appropriate type of data access to be generated.
15.1.1
Features
The block name includes these distinctive features: * External bus controller with four 8-bit ports A,B, E, and K * Data and data direction registers for ports A, B, E, and K when used as general-purpose I/O * Control register to enable/disable alternate functions on ports E and K * Mode control register * Control register to enable/disable pull resistors on ports A, B, E, and K * Control register to enable/disable reduced output drive on ports A, B, E, and K * Control register to configure external clock behavior * Control register to configure IRQ pin operation * Logic to capture and synchronize external interrupt pin inputs
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 395
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
REGS
Port K
ADDR
PK[7:0]/ECS/XCS/X[19:14]
Internal Bus
Data[15:0]
EXT BUS I/F CTL
ADDR DATA
Port A
Addr[19:0]
PA[7:0]/A[15:8]/ D[15:8]/D[7:0]
(Control)
Port B
ADDR
PB[7:0]/A[7:0]/ D[7:0]
DATA
PE[7:2]/NOACC/ IPIPE1/MODB/CLKTO IPIPE0/MODA/ ECLK/ LSTRB/TAGLO R/W PE1/IRQ PE0/XIRQ
ECLK CTL
CPU pipe info IRQ interrupt XIRQ interrupt
PIPE CTL IRQ CTL TAG CTL
mode
BDM tag info
Port E
BKGD
BKGD/MODC/TAGHI
Control signal(s) Data signal (unidirectional) Data signal (bidirectional) Data bus (unidirectional) Data bus (bidirectional)
Figure 15-1. MEBI Block Diagram
MC9S12NE64 Data Sheet, Rev. 1.1 396 Freescale Semiconductor
External Signal Description
15.1.2
*
Modes of Operation
*
*
*
*
*
*
*
Normal expanded wide mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. This mode allows 16-bit external memory and peripheral devices to be interfaced to the system. Normal expanded narrow mode Ports A and B are configured as a 16-bit address bus and port A is multiplexed with 8-bit data. Port E provides bus control and status signals. This mode allows 8-bit external memory and peripheral devices to be interfaced to the system. Normal single-chip mode There is no external expansion bus in this mode. The processor program is executed from internal memory. Ports A, B, K, and most of E are available as general-purpose I/O. Special single-chip mode This mode is generally used for debugging single-chip operation, boot-strapping, or security related operations. The active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. There is no external expansion bus after reset in this mode. Emulation expanded wide mode Developers use this mode for emulation systems in which the users target application is normal expanded wide mode. Emulation expanded narrow mode Developers use this mode for emulation systems in which the users target application is normal expanded narrow mode. Special test mode Ports A and B are configured as a 16-bit multiplexed address and data bus and port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset. Special peripheral mode This mode is intended for Freescale Semiconductor factory testing of the system. The CPU is inactive and an external (tester) bus master drives address, data, and bus control signals.
15.2
External Signal Description
In typical implementations, the MEBI sub-block of the core interfaces directly with external system pins. Some pins may not be bonded out in all implementations. Table 15-1 outlines the pin names and functions and gives a brief description of their operation reset state of these pins and associated pull-ups or pull-downs is dependent on the mode of operation and on the integration of this block at the chip level (chip dependent).
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 397
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
.
Table 15-1. External System Pins Associated With MEBI
Pin Name Pin Functions MODC BKGD TAGHI Description At the rising edge on RESET, the state of this pin is registered into the MODC bit to set the mode. (This pin always has an internal pullup.) Pseudo open-drain communication pin for the single-wire background debug mode. There is an internal pull-up resistor on this pin. When instruction tagging is on, a 0 at the falling edge of E tags the high half of the instruction word being read into the instruction queue. General-purpose I/O pins, see PORTA and DDRA registers. High-order address lines multiplexed during ECLK low. Outputs except in special peripheral mode where they are inputs from an external tester system. High-order bidirectional data lines multiplexed during ECLK high in expanded wide modes, special peripheral mode, and visible internal accesses (IVIS = 1) in emulation expanded narrow mode. Direction of data transfer is generally indicated by R/W. Alternate high-order and low-order bytes of the bidirectional data lines multiplexed during ECLK high in expanded narrow modes and narrow accesses in wide modes. Direction of data transfer is generally indicated by R/W. General-purpose I/O pins, see PORTB and DDRB registers. Low-order address lines multiplexed during ECLK low. Outputs except in special peripheral mode where they are inputs from an external tester system. Low-order bidirectional data lines multiplexed during ECLK high in expanded wide modes, special peripheral mode, and visible internal accesses (with IVIS = 1) in emulation expanded narrow mode. Direction of data transfer is generally indicated by R/W. General-purpose I/O pin, see PORTE and DDRE registers. CPU No Access output. Indicates whether the current cycle is a free cycle. Only available in expanded modes. At the rising edge of RESET, the state of this pin is registered into the MODB bit to set the mode. General-purpose I/O pin, see PORTE and DDRE registers. Instruction pipe status bit 1, enabled by PIPOE bit in PEAR. System clock test output. Only available in special modes. PIPOE = 1 overrides this function. The enable for this function is in the clock module. At the rising edge on RESET, the state of this pin is registered into the MODA bit to set the mode. General-purpose I/O pin, see PORTE and DDRE registers. Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.
BKGD/MODC/ TAGHI
PA7/A15/D15/D7 thru PA0/A8/D8/D0
PA7-PA0 A15-A8 D15-D8
D15/D7 thru D8/D0 PB7/A7/D7 thru PB0/A0/D0 PB7-PB0 A7-A0 D7-D0
PE7/NOACC
PE7 NOACC
PE6/IPIPE1/ MODB/CLKTO
MODB PE6 IPIPE1 CLKTO
PE5/IPIPE0/MODA
MODA PE5 IPIPE0
MC9S12NE64 Data Sheet, Rev. 1.1 398 Freescale Semiconductor
Memory Map and Register Definition
Table 15-1. External System Pins Associated With MEBI (continued)
Pin Name PE4/ECLK Pin Functions PE4 ECLK Description General-purpose I/O pin, see PORTE and DDRE registers. Bus timing reference clock, can operate as a free-running clock at the system clock rate or to produce one low-high clock per visible access, with the high period stretched for slow accesses. ECLK is controlled by the NECLK bit in PEAR, the IVIS bit in MODE, and the ESTR bit in EBICTL. General-purpose I/O pin, see PORTE and DDRE registers. Low strobe bar, 0 indicates valid data on D7-D0. In special peripheral mode, this pin is an input indicating the size of the data transfer (0 = 16-bit; 1 = 8-bit). In expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue. General-purpose I/O pin, see PORTE and DDRE registers. Read/write, indicates the direction of internal data transfers. This is an output except in special peripheral mode where it is an input. General-purpose input-only pin, can be read even if IRQ enabled. Maskable interrupt request, can be level sensitive or edge sensitive. General-purpose input-only pin. Non-maskable interrupt input. General-purpose I/O pin, see PORTK and DDRK registers. Emulation chip select General-purpose I/O pin, see PORTK and DDRK registers. External data chip select General-purpose I/O pins, see PORTK and DDRK registers. Memory expansion addresses
PE3/LSTRB/ TAGLO
PE3 LSTRB SZ8 TAGLO
PE2/R/W
PE2 R/W
PE1/IRQ
PE1 IRQ
PE0/XIRQ
PE0 XIRQ
PK7/ECS
PK7 ECS
PK6/XCS
PK6 XCS
PK5/X19 thru PK0/X14
PK5-PK0 X19-X14
Detailed descriptions of these pins can be found in the device overview chapter.
15.3
Memory Map and Register Definition
A summary of the registers associated with the MEBI sub-block is shown in Table 15-2. Detailed descriptions of the registers and bits are given in the subsections that follow. On most chips the registers are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 399
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.1
Module Memory Map
Table 15-2. MEBI Memory Map
Address Offset 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x001E 0x00032 0x00033 Port A Data Register (PORTA) Port B Data Register (PORTB) Data Direction Register A (DDRA) Data Direction Register B (DDRB) Reserved Reserved Reserved Reserved Port E Data Register (PORTE) Data Direction Register E (DDRE) Port E Assignment Register (PEAR) Mode Register (MODE) Pull Control Register (PUCR) Reduced Drive Register (RDRIV) External Bus Interface Control Register (EBICTL) Reserved IRQ Control Register (IRQCR) Port K Data Register (PORTK) Data Direction Register K (DDRK) Use Access R/W R/W R/W R/W R R R R R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
15.3.2
15.3.2.1
Register Descriptions
Port A Data Register (PORTA)
7 6 5 4 3 2 1 0
R Bit 7 W Reset Single Chip 0 PA7 0 PA6 AB/DB14 0 PA5 AB/DB13 0 PA4 AB/DB12 0 PA3 AB/DB11 0 PA2 AB/DB10 0 PA1 AB/DB9 AB9 and DB9/DB1 0 PA0 AB/DB8 AB8 and DB8/DB0 6 5 4 3 2 1 Bit 0
Expanded Wide, Emulation Narrow with AB/DB15 IVIS, and Peripheral
Expanded Narrow AB15 and AB14 and AB13 and AB12 and AB11 and AB10 and DB15/DB7 DB14/DB6 DB13/DB5 DB12/DB4 DB11/DB3 DB10/DB2
Figure 15-2. Port A Data Register (PORTA)
MC9S12NE64 Data Sheet, Rev. 1.1 400 Freescale Semiconductor
Memory Map and Register Definition
Read: Anytime when register is in the map Write: Anytime when register is in the map Port A bits 7 through 0 are associated with address lines A15 through A8 respectively and data lines D15/D7 through D8/D0 respectively. When this port is not used for external addresses such as in single-chip mode, these pins can be used as general-purpose I/O. Data direction register A (DDRA) determines the primary direction of each pin. DDRA also determines the source of data for a read of PORTA. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE To ensure that you read the value present on the PORTA pins, always wait at least one cycle after writing to the DDRA register before reading from the PORTA register.
15.3.2.2
Port B Data Register (PORTB)
7 6 5 4 3 2 1 0
R Bit 7 W Reset Single Chip Expanded Wide, Emulation Narrow with IVIS, and Peripheral Expanded Narrow 0 PB7 AB/DB7 AB7 0 PB6 AB/DB6 AB6 0 PB5 AB/DB5 AB5 0 PB4 AB/DB4 AB4 0 PB3 AB/DB3 AB3 0 PB2 AB/DB2 AB2 0 PB1 AB/DB1 AB1 0 PB0 AB/DB0 AB0 6 5 4 3 2 1 Bit 0
Figure 15-3. Port A Data Register (PORTB)
Read: Anytime when register is in the map Write: Anytime when register is in the map Port B bits 7 through 0 are associated with address lines A7 through A0 respectively and data lines D7 through D0 respectively. When this port is not used for external addresses, such as in single-chip mode, these pins can be used as general-purpose I/O. Data direction register B (DDRB) determines the primary direction of each pin. DDRB also determines the source of data for a read of PORTB. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE To ensure that you read the value present on the PORTB pins, always wait at least one cycle after writing to the DDRB register before reading from the PORTB register.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 401
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.2.3
Data Direction Register A (DDRA)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-4. Data Direction Register A (DDRA)
Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port A. When port A is operating as a general-purpose I/O port, DDRA determines the primary direction for each port A pin. A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTA register. If the DDR bit is 0 (input) the buffered pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control signals.
Table 15-3. DDRA Field Descriptions
Field 7:0 DDRA Description Data Direction Port A 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output
MC9S12NE64 Data Sheet, Rev. 1.1 402 Freescale Semiconductor
Memory Map and Register Definition
15.3.2.4
Data Direction Register B (DDRB)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-5. Data Direction Register B (DDRB)
Read: Anytime when register is in the map Write: Anytime when register is in the map This register controls the data direction for port B. When port B is operating as a general-purpose I/O port, DDRB determines the primary direction for each port B pin. A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTB register. If the DDR bit is 0 (input) the buffered pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. It is reset to 0x00 so the DDR does not override the three-state control signals.
Table 15-4. DDRB Field Descriptions
Field 7:0 DDRB Description Data Direction Port B 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 403
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.2.5
Reserved Registers
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-6. Reserved Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-7. Reserved Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-8. Reserved Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-9. Reserved Register
These register locations are not used (reserved). All unused registers and bits in this block return logic 0s when read. Writes to these registers have no effect. These registers are not in the on-chip map in special peripheral mode.
MC9S12NE64 Data Sheet, Rev. 1.1 404 Freescale Semiconductor
Memory Map and Register Definition
15.3.2.6
Port E Data Register (PORTE)
7 6 5 4 3 2 1 0
R Bit 7 W Reset Alternate Pin Function 0 NOACC 0 MODB or IPIPE1 or CLKTO 0 MODA or IPIPE0 0 ECLK 0 LSTRB or TAGLO 0 R/W 6 5 4 3 2
Bit 1
Bit 0
u IRQ
u XIRQ
= Unimplemented or Reserved
u = Unaffected by reset
Figure 15-10. Port E Data Register (PORTE)
Read: Anytime when register is in the map Write: Anytime when register is in the map Port E is associated with external bus control signals and interrupt inputs. These include mode select (MODB/IPIPE1, MODA/IPIPE0), E clock, size (LSTRB/TAGLO), read/write (R/W), IRQ, and XIRQ. When not used for one of these specific functions, port E pins 7:2 can be used as general-purpose I/O and pins 1:0 can be used as general-purpose input. The port E assignment register (PEAR) selects the function of each pin and DDRE determines whether each pin is an input or output when it is configured to be general-purpose I/O. DDRE also determines the source of data for a read of PORTE. Some of these pins have software selectable pull resistors. IRQ and XIRQ can only be pulled up whereas the polarity of the PE7, PE4, PE3, and PE2 pull resistors are determined by chip integration. Please refer to the device overview chapter (Signal Property Summary) to determine the polarity of these resistors. A single control bit enables the pull devices for all of these pins when they are configured as inputs. This register is not in the on-chip map in special peripheral mode or in expanded modes when the EME bit is set. Therefore, these accesses will be echoed externally. NOTE It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from being inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling as outputs. NOTE To ensure that you read the value present on the PORTE pins, always wait at least one cycle after writing to the DDRE register before reading from the PORTE register.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 405
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.2.7
Data Direction Register E (DDRE)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 6 5 4 3 Bit 2
0
0
0
0
= Unimplemented or Reserved
Figure 15-11. Data Direction Register E (DDRE)
Read: Anytime when register is in the map Write: Anytime when register is in the map Data direction register E is associated with port E. For bits in port E that are configured as general-purpose I/O lines, DDRE determines the primary direction of each of these pins. A 1 causes the associated bit to be an output and a 0 causes the associated bit to be an input. Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of whether the alternate interrupt function is enabled. The value in a DDR bit also affects the source of data for reads of the corresponding PORTE register. If the DDR bit is 0 (input) the buffered pin input state is read. If the DDR bit is 1 (output) the associated port data register bit state is read. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. Also, it is not in the map in expanded modes while the EME control bit is set.
Table 15-5. DDRE Field Descriptions
Field 7:2 DDRE Description Data Direction Port E 0 Configure the corresponding I/O pin as an input 1 Configure the corresponding I/O pin as an output Note: It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling as outputs.
MC9S12NE64 Data Sheet, Rev. 1.1 406 Freescale Semiconductor
Memory Map and Register Definition
15.3.2.8
Port E Assignment Register (PEAR)
7 6 5 4 3 2 1 0
R NOACCE W Reset Special Single Chip Special Test Peripheral Emulation Expanded Narrow Emulation Expanded Wide Normal Single Chip Normal Expanded Narrow Normal Expanded Wide 0 0 0 1 1 0 0 0
0 PIPOE NECLK LSTRE RDWE
0
0
0 0 0 0 0 0 0 0
0 1 0 1 1 0 0 0
0 0 0 0 0 1 0 0
0 1 0 1 1 0 0 0
0 1 0 1 1 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 15-12. Port E Assignment Register (PEAR)
Read: Anytime (provided this register is in the map). Write: Each bit has specific write conditions. Please refer to the descriptions of each bit on the following pages. Port E serves as general-purpose I/O or as system and bus control signals. The PEAR register is used to choose between the general-purpose I/O function and the alternate control functions. When an alternate control function is selected, the associated DDRE bits are overridden. The reset condition of this register depends on the mode of operation because bus control signals are needed immediately after reset in some modes. In normal single-chip mode, no external bus control signals are needed so all of port E is configured for general-purpose I/O. In normal expanded modes, only the E clock is configured for its alternate bus control function and the other bits of port E are configured for general-purpose I/O. As the reset vector is located in external memory, the E clock is required for this access. R/W is only needed by the system when there are external writable resources. If the normal expanded system needs any other bus control signals, PEAR would need to be written before any access that needed the additional signals. In special test and emulation modes, IPIPE1, IPIPE0, E, LSTRB, and R/W are configured out of reset as bus control signals. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 407
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
Table 15-6. PEAR Field Descriptions
Field 7 NOACCE Description CPU No Access Output Enable Normal: write once Emulation: write never Special: write anytime 1 The associated pin (port E, bit 7) is general-purpose I/O. 0 The associated pin (port E, bit 7) is output and indicates whether the cycle is a CPU free cycle. This bit has no effect in single-chip or special peripheral modes. Pipe Status Signal Output Enable Normal: write once Emulation: write never Special: write anytime. 0 The associated pins (port E, bits 6:5) are general-purpose I/O. 1 The associated pins (port E, bits 6:5) are outputs and indicate the state of the instruction queue This bit has no effect in single-chip or special peripheral modes. No External E Clock Normal and special: write anytime Emulation: write never 0 The associated pin (port E, bit 4) is the external E clock pin. External E clock is free-running if ESTR = 0 1 The associated pin (port E, bit 4) is a general-purpose I/O pin. External E clock is available as an output in all modes. Low Strobe (LSTRB) Enable Normal: write once Emulation: write never Special: write anytime. 0 The associated pin (port E, bit 3) is a general-purpose I/O pin. 1 The associated pin (port E, bit 3) is configured as the LSTRB bus control output. If BDM tagging is enabled, TAGLO is multiplexed in on the rising edge of ECLK and LSTRB is driven out on the falling edge of ECLK. This bit has no effect in single-chip, peripheral, or normal expanded narrow modes. Note: LSTRB is used during external writes. After reset in normal expanded mode, LSTRB is disabled to provide an extra I/O pin. If LSTRB is needed, it should be enabled before any external writes. External reads do not normally need LSTRB because all 16 data bits can be driven even if the system only needs 8 bits of data. Read/Write Enable Normal: write once Emulation: write never Special: write anytime 0 The associated pin (port E, bit 2) is a general-purpose I/O pin. 1 The associated pin (port E, bit 2) is configured as the R/W pin This bit has no effect in single-chip or special peripheral modes. Note: R/W is used for external writes. After reset in normal expanded mode, R/W is disabled to provide an extra I/O pin. If R/W is needed it should be enabled before any external writes.
5 PIPOE
4 NECLK
3 LSTRE
2 RDWE
MC9S12NE64 Data Sheet, Rev. 1.1 408 Freescale Semiconductor
Memory Map and Register Definition
15.3.2.9
Mode Register (MODE)
7 6 5 4 3 2 1 0
R MODC W Reset Special Single Chip Emulation Expanded Narrow Special Test Emulation Expanded Wide Normal Single Chip Normal Expanded Narrow Peripheral Normal Expanded Wide 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MODB MODA
0 IVIS
0 EMK EME
0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0
0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0
0 1 0 1 0 0 0 0
= Unimplemented or Reserved
Figure 15-13. Mode Register (MODE)
Read: Anytime (provided this register is in the map). Write: Each bit has specific write conditions. Please refer to the descriptions of each bit on the following pages. The MODE register is used to establish the operating mode and other miscellaneous functions (i.e., internal visibility and emulation of port E and K). In special peripheral mode, this register is not accessible but it is reset as shown to system configuration features. Changes to bits in the MODE register are delayed one cycle after the write. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 409
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
Table 15-7. MODE Field Descriptions
Field 7:5 MOD[C:A] Description Mode Select Bits -- These bits indicate the current operating mode. If MODA = 1, then MODC, MODB, and MODA are write never. If MODC = MODA = 0, then MODC, MODB, and MODA are writable with the exception that you cannot change to or from special peripheral mode If MODC = 1, MODB = 0, and MODA = 0, then MODC is write never. MODB and MODA are write once, except that you cannot change to special peripheral mode. From normal single-chip, only normal expanded narrow and normal expanded wide modes are available. See Table 15-8 and Table 15-16. 3 IVIS Internal Visibility (for both read and write accesses) -- This bit determines whether internal accesses generate a bus cycle that is visible on the external bus. Normal: write once Emulation: write never Special: write anytime 0 No visibility of internal bus operations on external bus. 1 Internal bus operations are visible on external bus. Emulate Port K Normal: write once Emulation: write never Special: write anytime 0 PORTK and DDRK are in the memory map so port K can be used for general-purpose I/O. 1 If in any expanded mode, PORTK and DDRK are removed from the memory map. In single-chip modes, PORTK and DDRK are always in the map regardless of the state of this bit. In special peripheral mode, PORTK and DDRK are never in the map regardless of the state of this bit. Emulate Port E Normal and Emulation: write never Special: write anytime 0 PORTE and DDRE are in the memory map so port E can be used for general-purpose I/O. 1 If in any expanded mode or special peripheral mode, PORTE and DDRE are removed from the memory map. Removing the registers from the map allows the user to emulate the function of these registers externally. In single-chip modes, PORTE and DDRE are always in the map regardless of the state of this bit.
1 EMK
0 EME
MC9S12NE64 Data Sheet, Rev. 1.1 410 Freescale Semiconductor
Memory Map and Register Definition
Table 15-8. MODC, MODB, and MODA Write Capability1
MODC 0 0 0 0 1 MODB 0 0 1 1 0 MODA 0 1 0 1 0 Mode Special single chip Emulation narrow Special test Emulation wide Normal single chip MODx Write Capability MODC, MODB, and MODA write anytime but not to 1102 No write MODC, MODB, and MODA write anytime but not to 110(2) No write MODC write never, MODB and MODA write once but not to 110 No write No write No write
1 1 1
1 2
0 1 1
1 0 1
Normal expanded narrow Special peripheral Normal expanded wide
No writes to the MOD bits are allowed while operating in a secure mode. For more details, refer to the device overview chapter. If you are in a special single-chip or special test mode and you write to this register, changing to normal single-chip mode, then one allowed write to this register remains. If you write to normal expanded or emulation mode, then no writes remain.
15.3.2.10 Pull Control Register (PUCR)
7 6 5 4 3 2 1 0
R PUPKE W Reset1 1
0
0 PUPEE
0
0 PUPBE PUPAE 0
0
0
1
0
0
0
NOTES: 1. The default value of this parameter is shown. Please refer to the device overview chapter to determine the actual reset state of this register.
= Unimplemented or Reserved
Figure 15-14. Pull Control Register (PUCR)
Read: Anytime (provided this register is in the map). Write: Anytime (provided this register is in the map). This register is used to select pull resistors for the pins associated with the core ports. Pull resistors are assigned on a per-port basis and apply to any pin in the corresponding port that is currently configured as an input. The polarity of these pull resistors is determined by chip integration. Please refer to the device overview chapter to determine the polarity of these resistors.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 411
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally. NOTE These bits have no effect when the associated pin(s) are outputs. (The pull resistors are inactive.)
Table 15-9. PUCR Field Descriptions
Field 7 PUPKE 4 PUPEE Pull resistors Port K Enable 0 Port K pull resistors are disabled. 1 Enable pull resistors for port K input pins. Pull resistors Port E Enable 0 Port E pull resistors on bits 7, 4:0 are disabled. 1 Enable pull resistors for port E input pins bits 7, 4:0. Note: Pins 5 and 6 of port E have pull resistors which are only enabled during reset. This bit has no effect on these pins. Pull resistors Port B Enable 0 Port B pull resistors are disabled. 1 Enable pull resistors for all port B input pins. Pull resistors Port A Enable 0 Port A pull resistors are disabled. 1 Enable pull resistors for all port A input pins. Description
1 PUPBE 0 PUPAE
15.3.2.11 Reduced Drive Register (RDRIV)
7 6 5 4 3 2 1 0
R RDRK W Reset 0
0
0 RDPE
0
0 RDPB RDPA 0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-15. Reduced Drive Register (RDRIV)
Read: Anytime (provided this register is in the map) Write: Anytime (provided this register is in the map) This register is used to select reduced drive for the pins associated with the core ports. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading). This feature would be used on ports which have a light loading. The reduced drive function is independent of which function is being used on a particular port. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
MC9S12NE64 Data Sheet, Rev. 1.1 412 Freescale Semiconductor
Memory Map and Register Definition
Table 15-10. RDRIV Field Descriptions
Field 7 RDRK 4 RDPE 1 RDPB 0 RDPA Description Reduced Drive of Port K 0 All port K output pins have full drive enabled. 1 All port K output pins have reduced drive enabled. Reduced Drive of Port E 0 All port E output pins have full drive enabled. 1 All port E output pins have reduced drive enabled. Reduced Drive of Port B 0 All port B output pins have full drive enabled. 1 All port B output pins have reduced drive enabled. Reduced Drive of Ports A 0 All port A output pins have full drive enabled. 1 All port A output pins have reduced drive enabled.
15.3.2.12 External Bus Interface Control Register (EBICTL)
7 6 5 4 3 2 1 0
R W Reset: Peripheral All other modes
0
0
0
0
0
0
0 ESTR
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
= Unimplemented or Reserved
Figure 15-16. External Bus Interface Control Register (EBICTL)
Read: Anytime (provided this register is in the map) Write: Refer to individual bit descriptions below The EBICTL register is used to control miscellaneous functions (i.e., stretching of external E clock). This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
Table 15-11. EBICTL Field Descriptions
Field 0 ESTR Description E Clock Stretches -- This control bit determines whether the E clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. Normal and Emulation: write once Special: write anytime 0 E never stretches (always free running). 1 E stretches high during stretched external accesses and remains low during non-visible internal accesses. This bit has no effect in single-chip modes.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 413
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.2.13 Reserved Register
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-17. Reserved Register
This register location is not used (reserved). All bits in this register return logic 0s when read. Writes to this register have no effect. This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these accesses will be echoed externally.
15.3.2.14 IRQ Control Register (IRQCR)
7 6 5 4 3 2 1 0
R IRQE W Reset 0 1 IRQEN
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-18. IRQ Control Register (IRQCR)
Read: See individual bit descriptions below Write: See individual bit descriptions below
Table 15-12. IRQCR Field Descriptions
Field 7 IRQE Description IRQ Select Edge Sensitive Only Special modes: read or write anytime Normal and Emulation modes: read anytime, write once 0 IRQ configured for low level recognition. 1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt. External IRQ Enable Normal, emulation, and special modes: read or write anytime 0 External IRQ pin is disconnected from interrupt logic. 1 External IRQ pin is connected to interrupt logic. Note: When IRQEN = 0, the edge detect latch is disabled.
6 IRQEN
MC9S12NE64 Data Sheet, Rev. 1.1 414 Freescale Semiconductor
Memory Map and Register Definition
15.3.2.15 Port K Data Register (PORTK)
7 6 5 4 3 2 1 0
R Bit 7 W Reset Alternate Pin Function 0 ECS 0 XCS 0 XAB19 0 XAB18 0 XAB17 0 XAB16 0 XAB15 0 XAB14 6 5 4 3 2 1 Bit 0
Figure 15-19. Port K Data Register (PORTK)
Read: Anytime Write: Anytime This port is associated with the internal memory expansion emulation pins. When the port is not enabled to emulate the internal memory expansion, the port pins are used as general-purpose I/O. When port K is operating as a general-purpose I/O port, DDRK determines the primary direction for each port K pin. A 1 causes the associated port pin to be an output and a 0 causes the associated pin to be a high-impedance input. The value in a DDR bit also affects the source of data for reads of the corresponding PORTK register. If the DDR bit is 0 (input) the buffered pin input is read. If the DDR bit is 1 (output) the output of the port data register is read. This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set. Therefore, these accesses will be echoed externally. When inputs, these pins can be selected to be high impedance or pulled up, based upon the state of the PUPKE bit in the PUCR register.
Table 15-13. PORTK Field Descriptions
Field 7 Port K, Bit 7 Description Port K, Bit 7 -- This bit is used as an emulation chip select signal for the emulation of the internal memory expansion, or as general-purpose I/O, depending upon the state of the EMK bit in the MODE register. While this bit is used as a chip select, the external bit will return to its de-asserted state (VDD) for approximately 1/4 cycle just after the negative edge of ECLK, unless the external access is stretched and ECLK is free-running (ESTR bit in EBICTL = 0). See the MMC block description chapter for additional details on when this signal will be active. Port K, Bit 6 -- This bit is used as an external chip select signal for most external accesses that are not selected by ECS (see the MMC block description chapter for more details), depending upon the state the of the EMK bit in the MODE register. While this bit is used as a chip select, the external pin will return to its deasserted state (VDD) for approximately 1/4 cycle just after the negative edge of ECLK, unless the external access is stretched and ECLK is free-running (ESTR bit in EBICTL = 0).
6 Port K, Bit 6
5:0 Port K, Bits 5:0 -- These six bits are used to determine which FLASH/ROM or external memory array page Port K, Bits 5:0 is being accessed. They can be viewed as expanded addresses XAB19-XAB14 of the 20-bit address used to access up to1M byte internal FLASH/ROM or external memory array. Alternatively, these bits can be used for general-purpose I/O depending upon the state of the EMK bit in the MODE register.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 415
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
15.3.2.16 Port K Data Direction Register (DDRK)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 6 5 4 3 2 1 Bit 0
Figure 15-20. Port K Data Direction Register (DDRK)
Read: Anytime Write: Anytime This register determines the primary direction for each port K pin configured as general-purpose I/O. This register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is set. Therefore, these accesses will be echoed externally.
Table 15-14. EBICTL Field Descriptions
Field 7:0 DDRK Description Data Direction Port K Bits 0 Associated pin is a high-impedance input 1 Associated pin is an output Note: It is unwise to write PORTK and DDRK as a word access. If you are changing port K pins from inputs to outputs, the data may have extra transitions during the write. It is best to initialize PORTK before enabling as outputs. Note: To ensure that you read the correct value from the PORTK pins, always wait at least one cycle after writing to the DDRK register before reading from the PORTK register.
15.4
15.4.1
Functional Description
Detecting Access Type from External Signals
The external signals LSTRB, R/W, and AB0 indicate the type of bus access that is taking place. Accesses to the internal RAM module are the only type of access that would produce LSTRB = AB0 = 1, because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these cases the data for the address that was accessed is on the low half of the data bus and the data for address + 1 is on the high half of the data bus. This is summarized in Table 15-15.
Table 15-15. Access Type vs. Bus Control Pins
LSTRB 1 0 1 0 0 AB0 0 1 0 1 0 R/W 1 1 0 0 1 Type of Access 8-bit read of an even address 8-bit read of an odd address 8-bit write of an even address 8-bit write of an odd address 16-bit read of an even address
MC9S12NE64 Data Sheet, Rev. 1.1 416 Freescale Semiconductor
Functional Description
Table 15-15. Access Type vs. Bus Control Pins
LSTRB 1 0 1 AB0 1 0 1 R/W 1 0 0 Type of Access 16-bit read of an odd address (low/high data swapped) 16-bit write to an even address 16-bit write to an odd address (low/high data swapped)
15.4.2
Stretched Bus Cycles
In order to allow fast internal bus cycles to coexist in a system with slower external memory resources, the HCS12 supports the concept of stretched bus cycles (module timing reference clocks for timers and baud rate generators are not affected by this stretching). Control bits in the MISC register in the MMC sub-block of the core specify the amount of stretch (0, 1, 2, or 3 periods of the internal bus-rate clock). While stretching, the CPU state machines are all held in their current state. At this point in the CPU bus cycle, write data would already be driven onto the data bus so the length of time write data is valid is extended in the case of a stretched bus cycle. Read data would not be captured by the system until the E clock falling edge. In the case of a stretched bus cycle, read data is not required until the specified setup time before the falling edge of the stretched E clock. The chip selects, and R/W signals remain valid during the period of stretching (throughout the stretched E high time). NOTE The address portion of the bus cycle is not stretched.
15.4.3
Modes of Operation
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during reset (Table 15-16). The MODC, MODB, and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are latched into these bits on the rising edge of the reset signal.
Table 15-16. Mode Selection
MODC 0 0 0 0 1 1 1 1 MODB 0 0 1 1 0 0 1 1 MODA 0 1 0 1 0 1 0 1 Mode Description Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes but a serial command is required to make BDM active. Emulation Expanded Narrow, BDM allowed Special Test (Expanded Wide), BDM allowed Emulation Expanded Wide, BDM allowed Normal Single Chip, BDM allowed Normal Expanded Narrow, BDM allowed Peripheral; BDM allowed but bus operations would cause bus conflicts (must not be used) Normal Expanded Wide, BDM allowed
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 417
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
There are two basic types of operating modes: 1. Normal modes: Some registers and bits are protected against accidental changes. 2. Special modes: Allow greater access to protected control registers and bits for special purposes such as testing. A system development and debug feature, background debug mode (BDM), is available in all modes. In special single-chip mode, BDM is active immediately after reset. Some aspects of Port E are not mode dependent. Bit 1 of Port E is a general purpose input or the IRQ interrupt input. IRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. Bit 0 of Port E is a general purpose input or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU's condition codes register but it is inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0 pins act as high-impedance mode select inputs during reset. The following paragraphs discuss the default bus setup and describe which aspects of the bus can be changed after reset on a per mode basis.
15.4.3.1
Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes, but must first be enabled for some operations by means of a BDM background command, then activated. 15.4.3.1.1 Normal Single-Chip Mode
There is no external expansion bus in this mode. All pins of Ports A, B and E are configured as general purpose I/O pins Port E bits 1 and 0 are available as general purpose input only pins with internal pull resistors enabled. All other pins of Port E are bidirectional I/O pins that are initially configured as high-impedance inputs with internal pull resistors enabled. Ports A and B are configured as high-impedance inputs with their internal pull resistors disabled. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single chip mode does not change the operation of the associated Port E pins. In normal single chip mode, the MODE register is writable one time. This allows a user program to change the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system.
MC9S12NE64 Data Sheet, Rev. 1.1 418 Freescale Semiconductor
Functional Description
15.4.3.1.2
Normal Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral devices to be interfaced to the MCU. Port E pins other than PE4/ECLK are configured as general purpose I/O pins (initially high-impedance inputs with internal pull resistors enabled). Control bits PIPOE, NECLK, LSTRE, and RDWE in the PEAR register can be used to configure Port E pins to act as bus control outputs instead of general purpose I/O pins. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. Development systems where pipe status signals are monitored would typically use the special variation of this mode. The Port E bit 2 pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. The Port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing "1" to the LSTRE bit in PEAR. The default condition of this pin is a general purpose input because the LSTRB function is not needed in all expanded wide applications. The Port E bit 4 pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. The E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. 15.4.3.1.3 Normal Expanded Narrow Mode
This mode is used for lower cost production systems that use 8-bit wide external EPROMs or RAMs. Such systems take extra bus cycles to access 16-bit locations but this may be preferred over the extra cost of additional external memory devices. Ports A and B are configured as a 16-bit address bus and Port A is multiplexed with data. Internal visibility is not available in this mode because the internal cycles would need to be split into two 8-bit cycles. Since the PEAR register can only be written one time in this mode, use care to set all bits to the desired states during the single allowed write. The PE3/LSTRB pin is always a general purpose I/O pin in normal expanded narrow mode. Although it is possible to write the LSTRE bit in PEAR to "1" in this mode, the state of LSTRE is overridden and Port E bit 3 cannot be reconfigured as the LSTRB output. It is possible to enable the pipe status signals on Port E bits 6 and 5 by setting the PIPOE bit in PEAR, but it would be unusual to do so in this mode. LSTRB would also be needed to fully understand system activity. Development systems where pipe status signals are monitored would typically use special expanded wide mode or occasionally special expanded narrow mode.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 419
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
The PE4/ECLK pin is initially configured as ECLK output with stretch. The E clock output function depends upon the settings of the NECLK bit in the PEAR register, the IVIS bit in the MODE register and the ESTR bit in the EBICTL register. In normal expanded narrow mode, the E clock is available for use in external select decode logic or as a constant speed clock for use in the external application system. The PE2/R/W pin is initially configured as a general purpose input with an internal pull resistor enabled but this pin can be reconfigured as the R/W bus control signal by writing "1" to the RDWE bit in PEAR. If the expanded narrow system includes external devices that can be written such as RAM, the RDWE bit would need to be set before any attempt to write to an external location. If there are no writable resources in the external system, PE2 can be left as a general purpose I/O pin. 15.4.3.1.4 Emulation Expanded Wide Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. These signals allow external memory and peripheral devices to be interfaced to the MCU. These signals can also be used by a logic analyzer to monitor the progress of application programs. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. 15.4.3.1.5 Emulation Expanded Narrow Mode
Expanded narrow modes are intended to allow connection of single 8-bit external memory devices for lower cost systems that do not need the performance of a full 16-bit external data bus. Accesses to internal resources that have been mapped external (i.e. PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, PUCR, RDRIV) will be accessed with a 16-bit data bus on Ports A and B. Accesses of 16-bit external words to addresses which are normally mapped external will be broken into two separate 8-bit accesses using Port A as an 8-bit data bus. Internal operations continue to use full 16-bit data paths. They are only visible externally as 16-bit information if IVIS=1. Ports A and B are configured as multiplexed address and data output ports. During external accesses, address A15, data D15 and D7 are associated with PA7, address A0 is associated with PB0 and data D8 and D0 are associated with PA0. During internal visible accesses and accesses to internal resources that have been mapped external, address A15 and data D15 is associated with PA7 and address A0 and data D0 is associated with PB0. The bus control related pins in Port E (PE7/NOACC, PE6/MODB/IPIPE1, PE5/MODA/IPIPE0, PE4/ECLK, PE3/LSTRB/TAGLO, and PE2/R/W) are all configured to serve their bus control output functions rather than general purpose I/O. Notice that writes to the bus control enable bits in the PEAR register in emulation mode are restricted. The main difference between special modes and normal modes is that some of the bus control and system control signals cannot be written in emulation modes.
MC9S12NE64 Data Sheet, Rev. 1.1 420 Freescale Semiconductor
Functional Description
15.4.3.2
Special Operating Modes
There are two special operating modes that correspond to normal operating modes. These operating modes are commonly used in factory testing and system development. 15.4.3.2.1 Special Single-Chip Mode
When the MCU is reset in this mode, the background debug mode is enabled and active. The MCU does not fetch the reset vector and execute application code as it would in other modes. Instead the active background mode is in control of CPU execution and BDM firmware is waiting for additional serial commands through the BKGD pin. When a serial command instructs the MCU to return to normal execution, the system will be configured as described below unless the reset states of internal control registers have been changed through background commands after the MCU was reset. There is no external expansion bus after reset in this mode. Ports A and B are initially simple bidirectional I/O pins that are configured as high-impedance inputs with internal pull resistors disabled; however, writing to the mode select bits in the MODE register (which is allowed in special modes) can change this after reset. All of the Port E pins (except PE4/ECLK) are initially configured as general purpose high-impedance inputs with internal pull resistors enabled. PE4/ECLK is configured as the E clock output in this mode. The pins associated with Port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1, IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated control bits PIPOE, LSTRE and RDWE are reset to zero. Writing the opposite value into these bits in single chip mode does not change the operation of the associated Port E pins. Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock for use in the external application system. 15.4.3.2.2 Special Test Mode
In expanded wide modes, Ports A and B are configured as a 16-bit multiplexed address and data bus and Port E provides bus control and status signals. In special test mode, the write protection of many control bits is lifted so that they can be thoroughly tested without needing to go through reset.
15.4.3.3
Test Operating Mode
There is a test operating mode in which an external master, such as an I.C. tester, can control the on-chip peripherals. 15.4.3.3.1 Peripheral Mode
This mode is intended for factory testing of the MCU. In this mode, the CPU is inactive and an external (tester) bus master drives address, data and bus control signals in through Ports A, B and E. In effect, the whole MCU acts as if it was a peripheral under control of an external CPU. This allows faster testing of on-chip memory and peripherals than previous testing methods. Since the mode control register is not accessible in peripheral mode, the only way to change to another mode is to reset the MCU into a different
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 421
Chapter 15 Multiplexed External Bus Interface (MEBIV3)
mode. Background debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both functions.
15.4.4
Internal Visibility
Internal visibility is available when the MCU is operating in expanded wide modes or emulation narrow mode. It is not available in single-chip, peripheral or normal expanded narrow modes. Internal visibility is enabled by setting the IVIS bit in the MODE register. If an internal access is made while E, R/W, and LSTRB are configured as bus control outputs and internal visibility is off (IVIS=0), E will remain low for the cycle, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. When internal visibility is enabled (IVIS=1), certain internal cycles will be blocked from going external. During cycles when the BDM is selected, R/W will remain high, data will maintain its previous state, and address and LSTRB pins will be updated with the internal value. During CPU no access cycles when the BDM is not driving, R/W will remain high, and address, data and the LSTRB pins will remain at their previous state. NOTE When the system is operating in a secure mode, internal visibility is not available (i.e., IVIS = 1 has no effect). Also, the IPIPE signals will not be visible, regardless of operating mode. IPIPE1-IPIPE0 will display 0es if they are enabled. In addition, the MOD bits in the MODE control register cannot be written.
15.4.5
Low-Power Options
The MEBI does not contain any user-controlled options for reducing power consumption. The operation of the MEBI in low-power modes is discussed in the following subsections.
15.4.5.1
Operation in Run Mode
The MEBI does not contain any options for reducing power in run mode; however, the external addresses are conditioned to reduce power in single-chip modes. Expanded bus modes will increase power consumption.
15.4.5.2
Operation in Wait Mode
The MEBI does not contain any options for reducing power in wait mode.
15.4.5.3
Operation in Stop Mode
The MEBI will cease to function after execution of a CPU STOP instruction.
MC9S12NE64 Data Sheet, Rev. 1.1 422 Freescale Semiconductor
Chapter 16 Module Mapping Control (MMCV4)
16.1 Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12 core platform. The block diagram of the MMC is shown in Figure 16-1.
MMC SECURE BDM_UNSECURE STOP, WAIT SECURITY MMC_SECURE
ADDRESS DECODE READ & WRITE ENABLES CLOCKS, RESET MODE INFORMATION INTERNAL MEMORY EXPANSION REGISTERS PORT K INTERFACE MEMORY SPACE SELECT(S) PERIPHERAL SELECT EBI ALTERNATE ADDRESS BUS EBI ALTERNATE WRITE DATA BUS EBI ALTERNATE READ DATA BUS ALTERNATE ADDRESS BUS (BDM) CPU ADDRESS BUS CPU READ DATA BUS CPU WRITE DATA BUS CPU CONTROL BUS CONTROL ALTERNATE WRITE DATA BUS (BDM) ALTERNATE READ DATA BUS (BDM) CORE SELECT (S)
Figure 16-1. MMC Block Diagram
The MMC is the sub-module which controls memory map assignment and selection of internal resources and external space. Internal buses between the core and memories and between the core and peripherals is controlled in this module. The memory expansion is generated in this module.
16.1.1
*
Features
Registers for mapping of address space for on-chip RAM, EEPROM, and FLASH (or ROM) memory blocks and associated registers
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 423
Chapter 16 Module Mapping Control (MMCV4)
* * * * * * * * * *
Memory mapping control and selection based upon address decode and system operating mode Core address bus control Core data bus control and multiplexing Core security state decoding Emulation chip select signal generation (ECS) External chip select signal generation (XCS) Internal memory expansion External stretch and ROM mapping control functions via the MISC register Reserved registers for test purposes Configurable system memory options defined at integration of core into the system-on-a-chip (SoC).
16.1.2
Modes of Operation
Some of the registers operate differently depending on the mode of operation (i.e., normal expanded wide, special single chip, etc.). This is best understood from the register descriptions.
16.2
External Signal Description
All interfacing with the MMC sub-block is done within the core, it has no external signals.
16.3
Memory Map and Register Definition
A summary of the registers associated with the MMC sub-block is shown in Figure 16-2. Detailed descriptions of the registers and bits are given in the subsections that follow.
16.3.1
Module Memory Map
Table 16-1. MMC Memory Map
Address Offset Register Initialization of Internal RAM Position Register (INITRM) Initialization of Internal Registers Position Register (INITRG) Initialization of Internal EEPROM Position Register (INITEE) Miscellaneous System Control Register (MISC) Reserved . . Reserved . . . . . . Access R/W R/W R/W R/W -- -- -- --
MC9S12NE64 Data Sheet, Rev. 1.1 424 Freescale Semiconductor
Memory Map and Register Definition
Table 16-1. MMC Memory Map (continued)
Address Offset Register Memory Size Register 0 (MEMSIZ0) Memory Size Register 1 (MEMSIZ1) . . . . Program Page Index Register (PPAGE) Reserved R/W -- Access R R
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 425
Chapter 16 Module Mapping Control (MMCV4)
16.3.2
Name INITRM
Register Descriptions
Bit 7 R W RAM15 0 6 RAM14 5 RAM13 4 RAM12 3 RAM11 2 0 1 0 Bit 0 RAMHAL 0
INITRG
R W
REG14
REG13
REG12
REG11
0
0
INITEE
R W
EE15 0
EE14 0
EE13 0
EE12 0
EE11
0
0
EEON
MISC
R W
EXSTR1 3
EXSTR0 2
ROMHM 1
ROMON Bit 0
MTSTO
R W
Bit 7
6
5
4
MTST1
R W
Bit 7
6
5
4
3
2
1
Bit 0
MEMSIZ0
R REG_SW0 W
0
EEP_SW1 EEP_SW0
0
RAM_SW2 RAM_SW1 RAM_SW0
MEMSIZ1
R ROM_SW1 ROM_SW0 W
0
0
0
0
PAG_SW1 PAG_SW0
PPAGE
R W
0
0
PIX5 0
PIX4 0
PIX3 0
PIX2 0
PIX1 0
PIX0 0
Reserved
R W
0
0
= Unimplemented
Figure 16-2. MMC Register Summary
16.3.2.1
Initialization of Internal RAM Position Register (INITRM)
7 6 5 4 3 2 1 0
R RAM15 W Reset 0 0 0 0 1 RAM14 RAM13 RAM12 RAM11
0
0 RAMHAL
0
0
1
= Unimplemented or Reserved
Figure 16-3. Initialization of Internal RAM Position Register (INITRM)
Read: Anytime
MC9S12NE64 Data Sheet, Rev. 1.1 426 Freescale Semiconductor
Memory Map and Register Definition
Write: Once in normal and emulation modes, anytime in special modes NOTE Writes to this register take one cycle to go into effect. This register initializes the position of the internal RAM within the on-chip system memory map.
Table 16-2. INITRM Field Descriptions
Field Description
7:3 Internal RAM Map Position -- These bits determine the upper five bits of the base address for the system's RAM[15:11] internal RAM array. 0 RAMHAL RAM High-Align -- RAMHAL specifies the alignment of the internal RAM array. 0 Aligns the RAM to the lowest address (0x0000) of the mappable space 1 Aligns the RAM to the higher address (0xFFFF) of the mappable space
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 427
Chapter 16 Module Mapping Control (MMCV4)
16.3.2.2
Initialization of Internal Registers Position Register (INITRG)
7 6 5 4 3 2 1 0
R W Reset
0 REG14 0 0 REG13 0 REG12 0 REG11 0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-4. Initialization of Internal Registers Position Register (INITRG)
Read: Anytime Write: Once in normal and emulation modes and anytime in special modes This register initializes the position of the internal registers within the on-chip system memory map. The registers occupy either a 1K byte or 2K byte space and can be mapped to any 2K byte space within the first 32K bytes of the system's address space.
Table 16-3. INITRG Field Descriptions
Field Description
6:3 Internal Register Map Position -- These four bits in combination with the leading zero supplied by bit 7 of REG[14:11] INITRG determine the upper five bits of the base address for the system's internal registers (i.e., the minimum base address is 0x0000 and the maximum is 0x7FFF).
MC9S12NE64 Data Sheet, Rev. 1.1 428 Freescale Semiconductor
Memory Map and Register Definition
16.3.2.3
Initialization of Internal EEPROM Position Register (INITEE)
7 6 5 4 3 2 1 0
R EE15 W Reset1 -- -- -- -- -- EE14 EE13 EE12 EE11
0
0 EEON
--
--
--
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register. = Unimplemented or Reserved
Figure 16-5. Initialization of Internal EEPROM Position Register (INITEE)
Read: Anytime Write: The EEON bit can be written to any time on all devices. Bits E[11:15] are "write anytime in all modes" on most devices. On some devices, bits E[11:15] are "write once in normal and emulation modes and write anytime in special modes". See device overview chapter to determine the actual write access rights. NOTE Writes to this register take one cycle to go into effect. This register initializes the position of the internal EEPROM within the on-chip system memory map.
Table 16-4. INITEE Field Descriptions
Field 7:3 EE[15:11] 0 EEON Description Internal EEPROM Map Position -- These bits determine the upper five bits of the base address for the system's internal EEPROM array. Enable EEPROM -- This bit is used to enable the EEPROM memory in the memory map. 0 Disables the EEPROM from the memory map. 1 Enables the EEPROM in the memory map at the address selected by EE[15:11].
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 429
Chapter 16 Module Mapping Control (MMCV4)
16.3.2.4
Miscellaneous System Control Register (MISC)
7 6 5 4 3 2 1 0
R W Reset: Expanded or Emulation Reset: Peripheral or Single Chip Reset: Special Test
0
0
0
0 EXSTR1 EXSTR0 ROMHM ROMON --1 1 0
0 0 0
0 0 0
0 0 0
0 0 0
1 1 1
1 1 1
0 0 0
1. The reset state of this bit is determined at the chip integration level. = Unimplemented or Reserved
Figure 16-6. Miscellaneous System Control Register (MISC)
Read: Anytime Write: As stated in each bit description NOTE Writes to this register take one cycle to go into effect. This register initializes miscellaneous control functions.
Table 16-5. INITEE Field Descriptions
Field Description
3:2 External Access Stretch Bits 1 and 0 EXSTR[1:0] Write: once in normal and emulation modes and anytime in special modes This two-bit field determines the amount of clock stretch on accesses to the external address space as shown in Table 16-6. In single chip and peripheral modes these bits have no meaning or effect. 1 ROMHM FLASH EEPROM or ROM Only in Second Half of Memory Map Write: once in normal and emulation modes and anytime in special modes 0 The fixed page(s) of FLASH EEPROM or ROM in the lower half of the memory map can be accessed. 1 Disables direct access to the FLASH EEPROM or ROM in the lower half of the memory map. These physical locations of the FLASH EEPROM or ROM remain accessible through the program page window. ROMON -- Enable FLASH EEPROM or ROM Write: once in normal and emulation modes and anytime in special modes This bit is used to enable the FLASH EEPROM or ROM memory in the memory map. 0 Disables the FLASH EEPROM or ROM from the memory map. 1 Enables the FLASH EEPROM or ROM in the memory map.
0 ROMON
Table 16-6. External Stretch Bit Definition
Stretch Bit EXSTR1 0 0 1 1 Stretch Bit EXSTR0 0 1 0 1 MC9S12NE64 Data Sheet, Rev. 1.1 430 Freescale Semiconductor Number of E Clocks Stretched 0 1 2 3
Memory Map and Register Definition
16.3.2.5
Reserved Test Register 0 (MTST0)
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-7. Reserved Test Register 0 (MTST0)
Read: Anytime Write: No effect -- this register location is used for internal test purposes.
16.3.2.6
Reserved Test Register 1 (MTST1)
7 6 5 4 3 2 1 0
R W Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
= Unimplemented or Reserved
Figure 16-8. Reserved Test Register 1 (MTST1)
Read: Anytime Write: No effect -- this register location is used for internal test purposes.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 431
Chapter 16 Module Mapping Control (MMCV4)
16.3.2.7
Memory Size Register 0 (MEMSIZ0)
7 6 5 4 3 2 1 0
R REG_SW0 W Reset --
0
EEP_SW1
EEP_SW0
0
RAM_SW2
RAM_SW1
RAM_SW0
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 16-9. Memory Size Register 0 (MEMSIZ0)
Read: Anytime Write: Writes have no effect Reset: Defined at chip integration, see device overview section. The MEMSIZ0 register reflects the state of the register, EEPROM and RAM memory space configuration switches at the core boundary which are configured at system integration. This register allows read visibility to the state of these switches.
Table 16-7. MEMSIZ0 Field Descriptions
Field 7 REG_SW0 Description Allocated System Register Space 0 Allocated system register space size is 1K byte 1 Allocated system register space size is 2K byte
5:4 Allocated System EEPROM Memory Space -- The allocated system EEPROM memory space size is as EEP_SW[1:0] given in Table 16-8. 2 Allocated System RAM Memory Space -- The allocated system RAM memory space size is as given in RAM_SW[2:0] Table 16-9.
Table 16-8. Allocated EEPROM Memory Space
eep_sw1:eep_sw0 00 01 10 11 Allocated EEPROM Space 0K byte 2K bytes 4K bytes 8K bytes
Table 16-9. Allocated RAM Memory Space
ram_sw2:ram_sw0 000 001 010 011 100 Allocated RAM Space 2K bytes 4K bytes 6K bytes 8K bytes 10K bytes RAM Mappable Region 2K bytes 4K bytes 8K bytes
2
INITRM Bits Used RAM[15:11] RAM[15:12] RAM[15:13] RAM[15:13] RAM[15:14]
RAM Reset Base Address1 0x0800 0x0000 0x0800 0x0000 0x1800
8K bytes 16K bytes
2
MC9S12NE64 Data Sheet, Rev. 1.1 432 Freescale Semiconductor
Memory Map and Register Definition
Table 16-9. Allocated RAM Memory Space (continued)
ram_sw2:ram_sw0 101 110 111
1 2
Allocated RAM Space 12K bytes 14K bytes 16K bytes
RAM Mappable Region 16K bytes 2 16K bytes
2
INITRM Bits Used RAM[15:14] RAM[15:14] RAM[15:14]
RAM Reset Base Address1 0x1000 0x0800 0x0000
16K bytes
The RAM Reset BASE Address is based on the reset value of the INITRM register, 0x0009. Alignment of the Allocated RAM space within the RAM mappable region is dependent on the value of RAMHAL.
NOTE As stated, the bits in this register provide read visibility to the system physical memory space allocations defined at system integration. The actual array size for any given type of memory block may differ from the allocated size. Please refer to the device overview chapter for actual sizes.
16.3.2.8
Memory Size Register 1 (MEMSIZ1)
7 6 5 4 3 2 1 0
R ROM_SW1 W Reset --
ROM_SW0
0
0
0
0
PAG_SW1
PAG_SW0
--
--
--
--
--
--
--
= Unimplemented or Reserved
Figure 16-10. Memory Size Register 1 (MEMSIZ1)
Read: Anytime Write: Writes have no effect Reset: Defined at chip integration, see device overview section. The MEMSIZ1 register reflects the state of the FLASH or ROM physical memory space and paging switches at the core boundary which are configured at system integration. This register allows read visibility to the state of these switches.
Table 16-10. MEMSIZ0 Field Descriptions
Field Description
7:6 Allocated System FLASH or ROM Physical Memory Space -- The allocated system FLASH or ROM ROM_SW[1:0] physical memory space is as given in Table 16-11. 1:0 Allocated Off-Chip FLASH or ROM Memory Space -- The allocated off-chip FLASH or ROM memory space PAG_SW[1:0] size is as given in Table 16-12.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 433
Chapter 16 Module Mapping Control (MMCV4)
Table 16-11. Allocated FLASH/ROM Physical Memory Space
rom_sw1:rom_sw0 00 01 10 11 Allocated FLASH or ROM Space 0K byte 16K bytes 48K bytes(1) 64K bytes(1)
NOTES: 1. The ROMHM software bit in the MISC register determines the accessibility of the FLASH/ROM memory space. Please refer to Section 16.3.2.8, "Memory Size Register 1 (MEMSIZ1)," for a detailed functional description of the ROMHM bit.
Table 16-12. Allocated Off-Chip Memory Options
pag_sw1:pag_sw0 00 01 10 11 Off-Chip Space 876K bytes 768K bytes 512K bytes 0K byte On-Chip Space 128K bytes 256K bytes 512K bytes 1M byte
NOTE As stated, the bits in this register provide read visibility to the system memory space and on-chip/off-chip partitioning allocations defined at system integration. The actual array size for any given type of memory block may differ from the allocated size. Please refer to the device overview chapter for actual sizes.
16.3.2.9
Program Page Index Register (PPAGE)
7 6 5 4 3 2 1 0
R W Reset1
0
0 PIX5 PIX4 -- PIX3 -- PIX2 -- PIX1 -- PIX0 --
--
--
--
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the actual reset state of this register. = Unimplemented or Reserved
Figure 16-11. Program Page Index Register (PPAGE)
Read: Anytime Write: Determined at chip integration. Generally it's: "write anytime in all modes;" on some devices it will be: "write only in special modes." Check specific device documentation to determine which applies. Reset: Defined at chip integration as either 0x00 (paired with write in any mode) or 0x3C (paired with write only in special modes), see device overview chapter.
MC9S12NE64 Data Sheet, Rev. 1.1 434 Freescale Semiconductor
Functional Description
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF as defined in Table 16-14. CALL and RTC instructions have special access to read and write this register without using the address bus. NOTE Normal writes to this register take one cycle to go into effect. Writes to this register using the special access of the CALL and RTC instructions will be complete before the end of the associated instruction.
Table 16-13. MEMSIZ0 Field Descriptions
Field 5:0 PIX[5:0] Description Program Page Index Bits 5:0 -- These page index bits are used to select which of the 64 FLASH or ROM array pages is to be accessed in the program page window as shown in Table 16-14.
Table 16-14. Program Page Index Register Bits
PIX5 0 0 0 0 . . . . . 1 1 1 1 PIX4 0 0 0 0 . . . . . 1 1 1 1 PIX3 0 0 0 0 . . . . 1 1 1 1 PIX2 0 0 0 0 . . . . . 1 1 1 1 PIX1 0 0 1 1 . . . . . 0 0 1 1 PIX0 0 1 0 1 . . . . . 0 1 0 1 Program Space Selected 16K page 0 16K page 1 16K page 2 16K page 3 . . . . . 16K page 60 16K page 61 16K page 62 16K page 63
16.4
Functional Description
The MMC sub-block performs four basic functions of the core operation: bus control, address decoding and select signal generation, memory expansion, and security decoding for the system. Each aspect is described in the following subsections.
16.4.1
Bus Control
The MMC controls the address bus and data buses that interface the core with the rest of the system. This includes the multiplexing of the input data buses to the core onto the main CPU read data bus and control
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 435
Chapter 16 Module Mapping Control (MMCV4)
of data flow from the CPU to the output address and data buses of the core. In addition, the MMC manages all CPU read data bus swapping operations.
16.4.2
Address Decoding
As data flows on the core address bus, the MMC decodes the address information, determines whether the internal core register or firmware space, the peripheral space or a memory register or array space is being addressed and generates the correct select signal. This decoding operation also interprets the mode of operation of the system and the state of the mapping control registers in order to generate the proper select. The MMC also generates two external chip select signals, emulation chip select (ECS) and external chip select (XCS).
16.4.2.1
Select Priority and Mode Considerations
Although internal resources such as control registers and on-chip memory have default addresses, each can be relocated by changing the default values in control registers. Normally, I/O addresses, control registers, vector spaces, expansion windows, and on-chip memory are mapped so that their address ranges do not overlap. The MMC will make only one select signal active at any given time. This activation is based upon the priority outlined in Table 16-15. If two or more blocks share the same address space, only the select signal for the block with the highest priority will become active. An example of this is if the registers and the RAM are mapped to the same space, the registers will have priority over the RAM and the portion of RAM mapped in this shared space will not be accessible. The expansion windows have the lowest priority. This means that registers, vectors, and on-chip memory are always visible to a program regardless of the values in the page select registers.
Table 16-15. Select Signal Priority
Priority Highest ... ... ... ... Lowest Address Space BDM (internal to core) firmware or register space Internal register space RAM memory block EEPROM memory block On-chip FLASH or ROM Remaining external space
In expanded modes, all address space not used by internal resources is by default external memory space. The data registers and data direction registers for ports A and B are removed from the on-chip memory map and become external accesses. If the EME bit in the MODE register (see MEBI block description chapter) is set, the data and data direction registers for port E are also removed from the on-chip memory map and become external accesses. In special peripheral mode, the first 16 registers associated with bus expansion are removed from the on-chip memory map (PORTA, PORTB, DDRA, DDRB, PORTE, DDRE, PEAR, MODE, PUCR, RDRIV, and the EBI reserved registers).
MC9S12NE64 Data Sheet, Rev. 1.1 436 Freescale Semiconductor
Functional Description
In emulation modes, if the EMK bit in the MODE register (see MEBI block description chapter) is set, the data and data direction registers for port K are removed from the on-chip memory map and become external accesses.
16.4.2.2
Emulation Chip Select Signal
When the EMK bit in the MODE register (see MEBI block description chapter) is set, port K bit 7 is used as an active-low emulation chip select signal, ECS. This signal is active when the system is in emulation mode, the EMK bit is set and the FLASH or ROM space is being addressed subject to the conditions outlined in Section 16.4.3.2, "Extended Address (XAB19:14) and ECS Signal Functionality." When the EMK bit is clear, this pin is used for general purpose I/O.
16.4.2.3
External Chip Select Signal
When the EMK bit in the MODE register (see MEBI block description chapter) is set, port K bit 6 is used as an active-low external chip select signal, XCS. This signal is active only when the ECS signal described above is not active and when the system is addressing the external address space. Accesses to unimplemented locations within the register space or to locations that are removed from the map (i.e., ports A and B in expanded modes) will not cause this signal to become active. When the EMK bit is clear, this pin is used for general purpose I/O.
16.4.3
Memory Expansion
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF in the physical memory space. The paged memory space can consist of solely on-chip memory or a combination of on-chip and off-chip memory. This partitioning is configured at system integration through the use of the paging configuration switches (pag_sw1:pag_sw0) at the core boundary. The options available to the integrator are as given in Table 16-16 (this table matches Table 16-12 but is repeated here for easy reference).
Table 16-16. Allocated Off-Chip Memory Options
pag_sw1:pag_sw0 00 01 10 11 Off-Chip Space 876K bytes 768K bytes 512K bytes 0K byte On-Chip Space 128K bytes 256K bytes 512K bytes 1M byte
Based upon the system configuration, the program page window will consider its access to be either internal or external as defined in Table 16-17.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 437
Chapter 16 Module Mapping Control (MMCV4)
Table 16-17. External/Internal Page Window Access
pag_sw1:pag_sw0 00 Partitioning 876K off-Chip, 128K on-Chip 768K off-chip, 256K on-chip 512K off-chip, 512K on-chip 0K off-chip, 1M on-chip PIX5:0 Value 0x0000-0x0037 0x0038-0x003F 0x0000-0x002F 0x0030-0x003F 0x0000-0x001F 0x0020-0x003F N/A 0x0000-0x003F Page Window Access External Internal External Internal External Internal External Internal
01
10
11
NOTE The partitioning as defined in Table 16-17 applies only to the allocated memory space and the actual on-chip memory sizes implemented in the system may differ. Please refer to the device overview chapter for actual sizes. The PPAGE register holds the page select value for the program page window. The value of the PPAGE register can be manipulated by normal read and write (some devices don't allow writes in some modes) instructions as well as the CALL and RTC instructions. Control registers, vector spaces, and a portion of on-chip memory are located in unpaged portions of the 64K byte physical address space. The stack and I/O addresses should also be in unpaged memory to make them accessible from any page. The starting address of a service routine must be located in unpaged memory because the 16-bit exception vectors cannot point to addresses in paged memory. However, a service routine can call other routines that are in paged memory. The upper 16K byte block of memory space (0xC000-0xFFFF) is unpaged. It is recommended that all reset and interrupt vectors point to locations in this area.
16.4.3.1
CALL and Return from Call Instructions
CALL and RTC are uninterruptable instructions that automate page switching in the program expansion window. CALL is similar to a JSR instruction, but the subroutine that is called can be located anywhere in the normal 64K byte address space or on any page of program expansion memory. CALL calculates and stacks a return address, stacks the current PPAGE value, and writes a new instruction-supplied value to PPAGE. The PPAGE value controls which of the 64 possible pages is visible through the 16K byte expansion window in the 64K byte memory map. Execution then begins at the address of the called subroutine. During the execution of a CALL instruction, the CPU: * Writes the old PPAGE value into an internal temporary register and writes the new instruction-supplied PPAGE value into the PPAGE register.
MC9S12NE64 Data Sheet, Rev. 1.1 438 Freescale Semiconductor
Functional Description
* * *
Calculates the address of the next instruction after the CALL instruction (the return address), and pushes this 16-bit value onto the stack. Pushes the old PPAGE value onto the stack. Calculates the effective address of the subroutine, refills the queue, and begins execution at the new address on the selected page of the expansion window.
This sequence is uninterruptable; there is no need to inhibit interrupts during CALL execution. A CALL can be performed from any address in memory to any other address. The PPAGE value supplied by the instruction is part of the effective address. For all addressing mode variations except indexed-indirect modes, the new page value is provided by an immediate operand in the instruction. In indexed-indirect variations of CALL, a pointer specifies memory locations where the new page value and the address of the called subroutine are stored. Using indirect addressing for both the new page value and the address within the page allows values calculated at run time rather than immediate values that must be known at the time of assembly. The RTC instruction terminates subroutines invoked by a CALL instruction. RTC unstacks the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction after the CALL. During the execution of an RTC instruction, the CPU: * Pulls the old PPAGE value from the stack * Pulls the 16-bit return address from the stack and loads it into the PC * Writes the old PPAGE value into the PPAGE register * Refills the queue and resumes execution at the return address This sequence is uninterruptable; an RTC can be executed from anywhere in memory, even from a different page of extended memory in the expansion window. The CALL and RTC instructions behave like JSR and RTS, except they use more execution cycles. Therefore, routinely substituting CALL/RTC for JSR/RTS is not recommended. JSR and RTS can be used to access subroutines that are on the same page in expanded memory. However, a subroutine in expanded memory that can be called from other pages must be terminated with an RTC. And the RTC unstacks a PPAGE value. So any access to the subroutine, even from the same page, must use a CALL instruction so that the correct PPAGE value is in the stack.
16.4.3.2
Extended Address (XAB19:14) and ECS Signal Functionality
If the EMK bit in the MODE register is set (see MEBI block description chapter) the PIX5:0 values will be output on XAB19:14 respectively (port K bits 5:0) when the system is addressing within the physical program page window address space (0x8000-0xBFFF) and is in an expanded mode. When addressing anywhere else within the physical address space (outside of the paging space), the XAB19:14 signals will be assigned a constant value based upon the physical address space selected. In addition, the active-low emulation chip select signal, ECS, will likewise function based upon the assigned memory allocation. In the cases of 48K byte and 64K byte allocated physical FLASH/ROM space, the operation of the ECS signal will additionally depend upon the state of the ROMHM bit (see Section 16.3.2.4, "Miscellaneous System Control Register (MISC)") in the MISC register. Table 16-18, Table 16-19, Table 16-20, and
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 439
Chapter 16 Module Mapping Control (MMCV4)
Table 16-21 summarize the functionality of these signals based upon the allocated memory configuration. Again, this signal information is only available externally when the EMK bit is set and the system is in an expanded mode.
Table 16-18. 0K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A N/A ROMHM N/A N/A N/A N/A ECS 1 1 0 0 XAB19:14 0x3D 0x3E PIX[5:0] 0x3F
Table 16-19. 16K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A N/A ROMHM N/A N/A N/A N/A ECS 1 1 1 0 XAB19:14 0x3D 0x3E PIX[5:0] 0x3F
Table 16-20. 48K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A External Internal N/A ROMHM N/A 0 1 N/A N/A N/A ECS 1 0 1 1 0 0 0x3F PIX[5:0] XAB19:14 0x3D 0x3E
Table 16-21. 64K Byte Physical FLASH/ROM Allocated
Address Space 0x0000-0x3FFF 0x4000-0x7FFF 0x8000-0xBFFF 0xC000-0xFFFF Page Window Access N/A N/A N/A N/A External Internal N/A ROMHM 0 1 0 1 N/A N/A N/A ECS 0 1 0 1 1 0 0 0x3F PIX[5:0] 0x3E XAB19:14 0x3D
MC9S12NE64 Data Sheet, Rev. 1.1 440 Freescale Semiconductor
Functional Description
A graphical example of a memory paging for a system configured as 1M byte on-chip FLASH/ROM with 64K allocated physical space is given in Figure 16-12.
0x0000 61
16K FLASH (UNPAGED)
0x4000
62
16K FLASH (UNPAGED) ONE 16K FLASH/ROM PAGE ACCESSIBLE AT A TIME (SELECTED BY PPAGE = 0 TO 63) 0x8000 0 1 2 3 59 60 61 62 63
16K FLASH (PAGED)
0xC000 63 These 16K FLASH/ROM pages accessible from 0x0000 to 0x7FFF if selected by the ROMHM bit in the MISC register. 16K FLASH (UNPAGED)
0xFF00 0xFFFF VECTORS NORMAL SINGLE CHIP
Figure 16-12. Memory Paging Example: 1M Byte On-Chip FLASH/ROM, 64K Allocation
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 441
Chapter 16 Module Mapping Control (MMCV4)
MC9S12NE64 Data Sheet, Rev. 1.1 442 Freescale Semiconductor
Chapter 17 Background Debug Module (BDMV4)
17.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12 core platform. A block diagram of the BDM is shown in Figure 17-1.
HOST SYSTEM BKGD 16-BIT SHIFT REGISTER
ADDRESS ENTAG BDMACT TRACE INSTRUCTION DECODE AND EXECUTION BUS INTERFACE AND CONTROL LOGIC DATA CLOCKS
SDV ENBDM
STANDARD BDM FIRMWARE LOOKUP TABLE
CLKSW
Figure 17-1. BDM Block Diagram
The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin. BDMV4 has enhanced capability for maintaining synchronization between the target and host while allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake signal to indicate when an operation is complete. The system is backwards compatible with older external interfaces.
17.1.1
* * * * * * * * *
Features
Single-wire communication with host development system BDMV4 (and BDM2): Enhanced capability for allowing more flexibility in clock rates BDMV4: SYNC command to determine communication rate BDMV4: GO_UNTIL command BDMV4: Hardware handshake protocol to increase the performance of the serial communication Active out of reset in special single-chip mode Nine hardware commands using free cycles, if available, for minimal CPU intervention Hardware commands not requiring active BDM 15 firmware commands execute from the standard BDM firmware lookup table
MC9S12NE64 Data Sheet, Rev. 1.1
Freescale Semiconductor
443
Chapter 17 Background Debug Module (BDMV4)
* * * *
Instruction tagging capability Software control of BDM operation during wait mode Software selectable clocks When secured, hardware commands are allowed to access the register space in special single-chip mode, if the FLASH and EEPROM erase tests fail.
17.1.2
Modes of Operation
BDM is available in all operating modes but must be enabled before firmware commands are executed. Some system peripherals may have a control bit which allows suspending the peripheral function during background debug mode.
17.1.2.1
Regular Run Modes
All of these operations refer to the part in run mode. The BDM does not provide controls to conserve power during run mode. * Normal operation General operation of the BDM is available and operates the same in all normal modes. * Special single-chip mode In special single-chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory. * Special peripheral mode BDM is enabled and active immediately out of reset. BDM can be disabled by clearing the BDMACT bit in the BDM status (BDMSTS) register. The BDM serial system should not be used in special peripheral mode. * Emulation modes General operation of the BDM is available and operates the same as in normal modes.
17.1.2.2
Secure Mode Operation
If the part is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to FLASH or EEPROM other than allowing erasure.
17.2
External Signal Description
A single-wire interface pin is used to communicate with the BDM system. Two additional pins are used for instruction tagging. These pins are part of the multiplexed external bus interface (MEBI) sub-block and all interfacing between the MEBI and BDM is done within the core interface boundary. Functional descriptions of the pins are provided below for completeness. * BKGD -- Background interface pin * TAGHI -- High byte instruction tagging pin * TAGLO -- Low byte instruction tagging pin
MC9S12NE64 Data Sheet, Rev. 1.1 444 Freescale Semiconductor
External Signal Description
* *
BKGD and TAGHI share the same pin. TAGLO and LSTRB share the same pin. NOTE Generally these pins are shared as described, but it is best to check the device overview chapter to make certain. All MCUs at the time of this writing have followed this pin sharing scheme.
17.2.1
BKGD -- Background Interface Pin
Debugging control logic communicates with external devices serially via the single-wire background interface pin (BKGD). During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode.
17.2.2
TAGHI -- High Byte Instruction Tagging Pin
This pin is used to tag the high byte of an instruction. When instruction tagging is on, a logic 0 at the falling edge of the external clock (ECLK) tags the high half of the instruction word being read into the instruction queue.
17.2.3
TAGLO -- Low Byte Instruction Tagging Pin
This pin is used to tag the low byte of an instruction. When instruction tagging is on and low strobe is enabled, a logic 0 at the falling edge of the external clock (ECLK) tags the low half of the instruction word being read into the instruction queue.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 445
Chapter 17 Background Debug Module (BDMV4)
17.3
Memory Map and Register Definition
A summary of the registers associated with the BDM is shown in Figure 17-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Detailed descriptions of the registers and associated bits are given in the subsections that follow.
17.3.1
Module Memory Map
Table 17-1. INT Memory Map
Register Address Reserved BDM Status Register (BDMSTS) Reserved BDM CCR Holding Register (BDMCCR) 7 8- BDM Internal Register Position (BDMINR) Reserved Use Access -- R/W -- R/W R --
MC9S12NE64 Data Sheet, Rev. 1.1 446 Freescale Semiconductor
Memory Map and Register Definition
17.3.2
Register Name Reserved
Register Descriptions
Bit 7 R W R W R W R W R W R W R W R W R W R W R W R W X 6 X 5 X 4 X 3 X 2 X 1 0 Bit 0 0
BDMSTS
ENBDM X
BDMACT
ENTAG X
SDV
TRACE
CLKSW X
UNSEC
0
Reserved
X
X
X
X
X
Reserved
X
X
X
X
X
X
X
X
Reserved
X
X
X
X
X
X
X
X
Reserved
X
X
X
X
X
X
X
X
BDMCCR
CCR7 0
CCR6 REG14
CCR5 REG13
CCR4 REG12
CCR3 REG11
CCR2 0
CCR1 0
CCR0 0
BDMINR
Reserved
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
Reserved
X
X
X
X
X
X
X
X
Reserved
X
X
X
X
X
X
X
X
= Unimplemented, Reserved X = Indeterminate 0
= Implemented (do not alter) = Always read zero
Figure 17-2. BDM Register Summary
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 447
Chapter 17 Background Debug Module (BDMV4)
17.3.2.1
BDM Status Register (BDMSTS)
7 6 5 4 3 2 1 0
R ENBDM W Reset: Special single-chip mode: Special peripheral mode: All other modes: 11 0 0 0
BDMACT ENTAG
SDV
TRACE CLKSW
UNSEC
0
1 1 1 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
02 0 0 0
0 0 0 0
= Unimplemented or Reserved
= Implemented (do not alter)
Figure 17-3. BDM Status Register (BDMSTS)
Note:
1
ENBDM is read as "1" by a debugging environment in Special single-chip mode when the device is not secured or secured but fully erased (Flash and EEPROM).This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed. UNSEC is read as "1" by a debugging environment in Special single-chip mode when the device is secured and fully erased, else it is "0" and can only be read if not secure (see also bit description).
2
Read: All modes through BDM operation Write: All modes but subject to the following: * BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM firmware lookup table upon exit from BDM active mode. * CLKSW can only be written via BDM hardware or standard BDM firmware write commands. * All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered by the BDM hardware or standard firmware lookup table as part of BDM command execution. * ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does not apply in special single-chip mode).
Table 17-2. BDMSTS Field Descriptions
Field 7 ENBDM Description Enable BDM -- This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are allowed. 0 BDM disabled 1 BDM enabled Note: ENBDM is set by the firmware immediately out of reset in special single-chip mode. In secure mode, this bit will not be set by the firmware until after the EEPROM and FLASH erase verify tests are complete. BDM Active Status -- This bit becomes set upon entering BDM. The standard BDM firmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map. 0 BDM not active 1 BDM active
6 BDMACT
MC9S12NE64 Data Sheet, Rev. 1.1 448 Freescale Semiconductor
Memory Map and Register Definition
Table 17-2. BDMSTS Field Descriptions (continued)
Field 5 ENTAG Description Tagging Enable -- This bit indicates whether instruction tagging in enabled or disabled. It is set when the TAGGO command is executed and cleared when BDM is entered. The serial system is disabled and the tag function enabled 16 cycles after this bit is written. BDM cannot process serial commands while tagging is active. 0 Tagging not enabled or BDM active 1 Tagging enabled Shift Data Valid -- This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a firmware read command or after data has been received as part of a firmware write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM firmware to control program flow execution. 0 Data phase of command not complete 1 Data phase of command is complete TRACE1 BDM Firmware Command is Being Executed -- This bit gets set when a BDM TRACE1 firmware command is first recognized. It will stay set as long as continuous back-to-back TRACE1 commands are executed. This bit will get cleared when the next command that is not a TRACE1 command is recognized. 0 TRACE1 command is not being executed 1 TRACE1 command is being executed Clock Switch -- The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware BDM command. A 150 cycle delay at the clock speed that is active during the data portion of the command will occur before the new clock source is guaranteed to be active. The start of the next BDM command uses the new clock for timing subsequent BDM communications. Table 17-3 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (Pll select from the clock and reset generator) bits. Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency restriction on the alternate clock which was required on previous versions. Refer to the device overview section to determine which clock connects to the alternate clock source input. Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new rate for the write command which changes it. Unsecure -- This bit is only writable in special single-chip mode from the BDM secure firmware and always gets reset to zero. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled and put into the memory map along with the standard BDM firmware lookup table. The secure BDM firmware lookup table verifies that the on-chip EEPROM and FLASH EEPROM are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted. 0 System is in a secured mode 1 System is in a unsecured mode Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip FLASH EEPROM. Note that if the user does not change the state of the bits to "unsecured" mode, the system will be secured again when it is next taken out of reset.
4 SDV
3 TRACE
2 CLKSW
1 UNSEC
Table 17-3. BDM Clock Sources
PLLSEL 0 0 CLKSW 0 1 Bus clock Bus clock BDMCLK
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 449
Chapter 17 Background Debug Module (BDMV4)
Table 17-3. BDM Clock Sources
PLLSEL 1 1 CLKSW 0 1 BDMCLK Alternate clock (refer to the device overview chapter to determine the alternate clock source) Bus clock dependent on the PLL
MC9S12NE64 Data Sheet, Rev. 1.1 450 Freescale Semiconductor
Memory Map and Register Definition
17.3.2.2
BDM CCR Holding Register (BDMCCR)
7 6 5 4 3 2 1 0
R CCR7 W Reset 0 0 0 0 0 0 0 0 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0
Figure 17-4. BDM CCR Holding Register (BDMCCR)
Read: All modes Write: All modes NOTE When BDM is made active, the CPU stores the value of the CCR register in the BDMCCR register. However, out of special single-chip reset, the BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR register. When entering background debug mode, the BDM CCR holding register is used to save the contents of the condition code register of the user's program. It is also used for temporary storage in the standard BDM firmware mode. The BDM CCR holding register can be written to modify the CCR value.
17.3.2.3
BDM Internal Register Position Register (BDMINR)
7 6 5 4 3 2 1 0
R W Reset
0
REG14
REG13
REG12
REG11
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-5. BDM Internal Register Position (BDMINR)
Read: All modes Write: Never
Table 17-4. BDMINR Field Descriptions
Field Description
6:3 Internal Register Map Position -- These four bits show the state of the upper five bits of the base address for REG[14:11] the system's relocatable register block. BDMINR is a shadow of the INITRG register which maps the register block to any 2K byte space within the first 32K bytes of the 64K byte address space.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 451
Chapter 17 Background Debug Module (BDMV4)
17.4
Functional Description
The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands, namely, hardware commands and firmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 17.4.3, "BDM Hardware Commands." Target system memory includes all memory that is accessible by the CPU. Firmware commands are used to read and write CPU resources and to exit from active background debug mode, see Section 17.4.4, "Standard BDM Firmware Commands." The CPU resources referred to are the accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC). Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted, see Section 17.4.3, "BDM Hardware Commands." Firmware commands can only be executed when the system is in active background debug mode (BDM).
17.4.1
Security
If the user resets into special single-chip mode with the system secured, a secured mode BDM firmware lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table. The secure BDM firmware verifies that the on-chip EEPROM and FLASH EEPROM are erased. This being the case, the UNSEC bit will get set. The BDM program jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and all BDM commands are allowed. If the EEPROM or FLASH do not verify as erased, the BDM firmware sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the firmware commands. This allows the BDM hardware to be used to erase the EEPROM and FLASH. After execution of the secure firmware, regardless of the results of the erase tests, the CPU registers, INITEE and PPAGE, will no longer be in their reset state.
17.4.2
Enabling and Activating BDM
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE. After being enabled, BDM is activated by one of the following1: * Hardware BACKGROUND command * BDM external instruction tagging mechanism * CPU BGND instruction * Breakpoint sub-block's force or tag mechanism2 When BDM is activated, the CPU finishes executing the current instruction and then begins executing the firmware in the standard BDM firmware lookup table. When BDM is activated by the breakpoint
1. BDM is enabled and active immediately out of special single-chip reset. 2. This method is only available on systems that have a a breakpoint or a debug sub-block. MC9S12NE64 Data Sheet, Rev. 1.1 452 Freescale Semiconductor
Functional Description
sub-block, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses 0xFF00 to 0xFFFF. BDM registers are mapped to addresses 0xFF00 to 0xFF07. The BDM uses these registers which are readable anytime by the BDM. However, these registers are not readable by user programs.
17.4.3
BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, EEPROM, FLASH EEPROM, I/O and control registers, and all external memory. Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for execution, although they can continue to be executed in this mode. When executing a hardware command, the BDM sub-block waits for a free CPU bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 453
Chapter 17 Background Debug Module (BDMV4)
The BDM hardware commands are listed in Table 17-5.
Table 17-5. Hardware Commands
Command BACKGROUND ACK_ENABLE ACK_DISABLE READ_BD_BYTE READ_BD_WORD READ_BYTE READ_WORD WRITE_BD_BYTE WRITE_BD_WORD WRITE_BYTE WRITE_WORD Opcode (hex) 90 D5 D6 E4 EC E0 E8 C4 CC C0 C8 Data None None None 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data out 16-bit address 16-bit data in 16-bit address 16-bit data in 16-bit address 16-bit data in 16-bit address 16-bit data in Description Enter background mode if firmware is enabled. If enabled, an ACK will be issued when the part enters active background mode. Enable handshake. Issues an ACK pulse after the command is executed. Disable handshake. This command does not issue an ACK pulse. Read from memory with standard BDM firmware lookup table in map. Odd address data on low byte; even address data on high byte. Read from memory with standard BDM firmware lookup table in map. Must be aligned access. Read from memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte. Read from memory with standard BDM firmware lookup table out of map. Must be aligned access. Write to memory with standard BDM firmware lookup table in map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table in map. Must be aligned access. Write to memory with standard BDM firmware lookup table out of map. Odd address data on low byte; even address data on high byte. Write to memory with standard BDM firmware lookup table out of map. Must be aligned access.
NOTE: If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the system memory map but share addresses with the application in memory. To distinguish between physical memory locations that share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map.
17.4.4
Standard BDM Firmware Commands
Firmware commands are used to access and manipulate CPU resources. The system must be in active BDM to execute standard BDM firmware commands, see Section 17.4.2, "Enabling and Activating BDM." Normal instruction execution is suspended while the CPU executes the firmware located in the standard BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM. As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become visible in the on-chip memory map at 0xFF00-0xFFFF, and the CPU begins executing the standard BDM
MC9S12NE64 Data Sheet, Rev. 1.1 454 Freescale Semiconductor
Functional Description
firmware. The standard BDM firmware watches for serial commands and executes them as they are received. The firmware commands are shown in Table 17-6.
Table 17-6. Firmware Commands
Command1 READ_NEXT READ_PC READ_D READ_X READ_Y READ_SP WRITE_NEXT WRITE_PC WRITE_D WRITE_X WRITE_Y WRITE_SP GO GO_UNTIL2 TRACE1 TAGGO
1
Opcode (hex) 62 63 64 65 66 67 42 43 44 45 46 47 08 0C 10 18
Data 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data out 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in 16-bit data in None None None None
Description Increment X by 2 (X = X + 2), then read word X points to. Read program counter. Read D accumulator. Read X index register. Read Y index register. Read stack pointer. Increment X by 2 (X = X + 2), then write word to location pointed to by X. Write program counter. Write D accumulator. Write X index register. Write Y index register. Write stack pointer. Go to user program. If enabled, ACK will occur when leaving active background mode. Go to user program. If enabled, ACK will occur upon returning to active background mode. Execute one user instruction then return to active BDM. If enabled, ACK will occur upon returning to active background mode. Enable tagging and go to user program. There is no ACK pulse related to this command.
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. 2 Both WAIT (with clocks to the S12 CPU core disabled) and STOP disable the ACK function. The GO_UNTIL command will not get an Acknowledge if one of these two CPU instructions occurs before the "UNTIL" instruction. This can be a problem for any instruction that uses ACK, but GO_UNTIL is a lot more difficult for the development tool to time-out.
17.4.5
BDM Command Structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. NOTE 8-bit reads return 16-bits of data, of which, only one byte will contain valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 455
Chapter 17 Background Debug Module (BDMV4)
NOTE 16-bit misaligned reads and writes are not allowed. If attempted, the BDM will ignore the least significant bit of the address and will assume an even address from the remaining bits. For hardware data read commands, the external host must wait 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For firmware read commands, the external host should wait 44 bus clock cycles after sending the command opcode and before attempting to obtain the read data. This includes the potential of an extra 7 cycles when the access is external with a narrow bus access (+1 cycle) and / or a stretch (+1, 2, or 3 cycles), (7 cycles could be needed if both occur). The 44 cycle wait allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. NOTE This timing has increased from previous BDM modules due to the new capability in which the BDM serial interface can potentially run faster than the bus. On previous BDM modules this extra time could be hidden within the serial time. For firmware write commands, the external host must wait 32 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The external host should wait 64 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM firmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM firmware lookup table. NOTE If the bus rate of the target processor is unknown or could be changing, it is recommended that the ACK (acknowledge function) be used to indicate when an operation is complete. When using ACK, the delay times are automated. Figure 17-6 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 x 16 target clock cycles.1
1. Target clock cycles are cycles measured using the target MCU's serial clock rate. See Section 17.4.6, "BDM Serial Interface," and Section 17.3.2.1, "BDM Status Register (BDMSTS)," for information on how serial clock rate is selected. MC9S12NE64 Data Sheet, Rev. 1.1 456 Freescale Semiconductor
Functional Description
8 BITS AT 16 TC/BIT HARDWARE READ COMMAND
16 BITS AT 16 TC/BIT ADDRESS
150-BC DELAY
16 BITS AT 16 TC/BIT DATA 150-BC DELAY NEXT COMMAND
HARDWARE WRITE
COMMAND 44-BC DELAY
ADDRESS
DATA
NEXT COMMAND
FIRMWARE READ
COMMAND
DATA 32-BC DELAY
NEXT COMMAND
FIRMWARE WRITE
COMMAND 64-BC DELAY
DATA
NEXT COMMAND
GO, TRACE
COMMAND
NEXT COMMAND
BC = BUS CLOCK CYCLES TC = TARGET CLOCK CYCLES
Figure 17-6. BDM Command Structure
17.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see Section 17.3.2.1, "BDM Status Register (BDMSTS)." This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Because R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 17-7 and that of target-to-host in Figure 17-8 and Figure 17-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Because the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 457
Chapter 17 Background Debug Module (BDMV4)
clock cycle earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 17-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. Because the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.
CLOCK TARGET SYSTEM
HOST TRANSMIT 1
HOST TRANSMIT 0 PERCEIVED START OF BIT TIME 10 CYCLES SYNCHRONIZATION UNCERTAINTY TARGET SENSES BIT EARLIEST START OF NEXT BIT
Figure 17-7. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 17-8 shows the host receiving a logic 1 from the target system. Because the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.
MC9S12NE64 Data Sheet, Rev. 1.1 458 Freescale Semiconductor
Functional Description
CLOCK TARGET SYSTEM
HOST DRIVE TO BKGD PIN TARGET SYSTEM SPEEDUP PULSE PERCEIVED START OF BIT TIME R-C RISE BKGD PIN
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 17-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 17-9 shows the host receiving a logic 0 from the target. Because the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time.
CLOCK TARGET SYS.
HOST DRIVE TO BKGD PIN TARGET SYS. DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD PIN
HIGH-IMPEDANCE SPEEDUP PULSE
10 CYCLES 10 CYCLES EARLIEST START OF NEXT BIT
HOST SAMPLES BKGD PIN
Figure 17-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 459
Chapter 17 Background Debug Module (BDMV4)
17.4.7
Serial Interface Hardware Handshake Protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Because the BDM clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This sub-section will describe the hardware handshake protocol. The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 17-10). This pulse is referred to as the ACK pulse. After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL, or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command and the related ACK pulse, because the command execution depends upon the CPU bus frequency, which in some cases could be very slow compared to the serial communication rate. This protocol allows a great flexibility for the POD designers, because it does not rely on any accurate time measurement or short response time to any event in the serial communication.
BDM CLOCK (TARGET MCU)
16 CYCLES TARGET TRANSMITS ACK PULSE HIGH-IMPEDANCE 32 CYCLES SPEEDUP PULSE MINIMUM DELAY FROM THE BDM COMMAND BKGD PIN EARLIEST START OF NEXT BIT HIGH-IMPEDANCE
16th TICK OF THE LAST COMMAD BIT
Figure 17-10. Target Acknowledge Pulse (ACK)
NOTE If the ACK pulse was issued by the target, the host assumes the previous command was executed. If the CPU enters WAIT or STOP prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending.
MC9S12NE64 Data Sheet, Rev. 1.1 460 Freescale Semiconductor
Functional Description
Figure 17-11 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed (free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form of a word and the host needs to determine which is the appropriate byte based on whether the address was odd or even.
TARGET HOST NEW BDM COMMAND HOST BDM ISSUES THE ACK PULSE (OUT OF SCALE) BDM EXECUTES THE READ_BYTE COMMAND TARGET
BKGD PIN
READ_BYTE HOST
BYTE ADDRESS TARGET
(2) BYTES ARE RETRIEVED
BDM DECODES THE COMMAND
Figure 17-11. Handshake Protocol at Command Level
Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK handshake pulse is initiated by the target MCU by issuing a falling edge in the BKGD pin. The hardware handshake protocol in Figure 17-10 specifies the timing when the BKGD pin is being driven, so the host should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin. NOTE The only place the BKGD pin can have an electrical conflict is when one side is driving low and the other side is issuing a speedup pulse (high). Other "highs" are pulled rather than driven. However, at low rates the time of the speedup pulse can become lengthy and so the potential conflict time becomes longer as well. The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to issue a new BDM command. When the CPU enters WAIT or STOP while the host issues a command that requires CPU execution (e.g., WRITE_BYTE), the target discards the incoming command due to the WAIT or STOP being detected. Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be issued in this case. After a certain time the host should decide to abort the ACK sequence in order to be free to issue a new command. Therefore, the protocol should provide a mechanism in which a command, and therefore a pending ACK, could be aborted. NOTE Differently from a regular BDM command, the ACK pulse does not provide a time out. This means that in the case of a WAIT or STOP instruction being executed, the ACK would be prevented from being issued. If not aborted, the ACK would remain pending indefinitely. See the handshake abort procedure described in Section 17.4.8, "Hardware Handshake Abort Procedure."
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 461
Chapter 17 Background Debug Module (BDMV4)
17.4.8
Hardware Handshake Abort Procedure
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 17.4.9, "SYNC -- Request Timed Reference Pulse," and assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been completed the host is free to issue new BDM commands. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a falling edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the falling edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not a read command the short abort pulse could be used. After a command is aborted the target assumes the next falling edge, after the abort pulse, is the first bit of a new BDM command. NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application. Because the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 17.4.9, "SYNC -- Request Timed Reference Pulse." Figure 17-12 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the command is aborted a new command could be issued by the host computer. NOTE Figure 17-12 does not represent the signals in a true timing scale
MC9S12NE64 Data Sheet, Rev. 1.1 462 Freescale Semiconductor
Functional Description
READ_BYTE CMD IS ABORTED BY THE SYNC REQUEST (OUT OF SCALE)
SYNC RESPONSE FROM THE TARGET (OUT OF SCALE)
BKGD PIN
READ_BYTE HOST
MEMORY ADDRESS TARGET
READ_STATUS HOST TARGET
NEW BDM COMMAND HOST TARGET
BDM DECODE AND STARTS TO EXECUTES THE READ_BYTE CMD
NEW BDM COMMAND
Figure 17-12. ACK Abort Procedure at the Command Level
Figure 17-13 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Because this is not a probable situation, the protocol does not prevent this conflict from happening.
AT LEAST 128 CYCLES BDM CLOCK (TARGET MCU) ACK PULSE TARGET MCU DRIVES TO BKGD PIN HOST DRIVES SYNC TO BKGD PIN HOST AND TARGET DRIVE TO BKGD PIN HOST SYNC REQUEST PULSE BKGD PIN HIGH-IMPEDANCE ELECTRICAL CONFLICT
SPEEDUP PULSE
16 CYCLES
Figure 17-13. ACK Pulse and SYNC Request Conflict
NOTE This information is being provided so that the MCU integrator will be aware that such a conflict could eventually occur. The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol. It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 463
Chapter 17 Background Debug Module (BDMV4)
The commands are described as follows: * ACK_ENABLE -- enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response. * ACK_DISABLE -- disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol. The default state of the BDM after reset is hardware handshake protocol disabled. All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 17.4.3, "BDM Hardware Commands," and Section 17.4.4, "Standard BDM Firmware Commands," for more information on the BDM commands. The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target because it is not recognized as a valid command. The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command could be aborted using the SYNC command. The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command. The TAGGO command will not issue an ACK pulse because this would interfere with the tagging function shared on the same pin.
MC9S12NE64 Data Sheet, Rev. 1.1 464 Freescale Semiconductor
Functional Description
17.4.9
SYNC -- Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (the lowest serial communication frequency is determined by the crystal oscillator or the clock chosen by CLKSW.) 2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. Remove all drive to the BKGD pin so it reverts to high impedance. 4. Listen to the BKGD pin for the sync response pulse. Upon detecting the SYNC request from the host, the target performs the following steps: 1. Discards any incomplete command received or bit retrieved. 2. Waits for BKGD to return to a logic 1. 3. Delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency. 5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next falling edge (issued by the host) as the start of a new BDM command or the start of new SYNC request. Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued.
17.4.10 Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM firmware and executes a single instruction in the user code. As soon as this has occurred, the CPU is forced to return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 465
Chapter 17 Background Debug Module (BDMV4)
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Upon return to standard BDM firmware execution, the program counter points to the first instruction in the interrupt service routine.
17.4.11 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity are reconstructible in real time or from trace history that is captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the CPU at a specific instruction. This is because execution already has begun by the time an operation is visible outside the system. A separate instruction tagging mechanism is provided for this purpose. The tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue, the CPU enters active BDM rather than executing the instruction. NOTE Tagging is disabled when BDM becomes active and BDM serial commands are not processed while tagging is active. Executing the BDM TAGGO command configures two system pins for tagging. The TAGLO signal shares a pin with the LSTRB signal, and the TAGHI signal shares a pin with the BKGD signal. Table 17-7 shows the functions of the two tagging pins. The pins operate independently, that is the state of one pin does not affect the function of the other. The presence of logic level 0 on either pin at the fall of the external clock (ECLK) performs the indicated function. High tagging is allowed in all modes. Low tagging is allowed only when low strobe is enabled (LSTRB is allowed only in wide expanded modes and emulation expanded narrow mode).
Table 17-7. Tag Pin Function
TAGHI 1 1 0 0 TAGLO 1 0 1 0 Tag No tag Low byte High byte Both bytes
17.4.12 Serial Communication Time-Out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any time-out limit. Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset.
MC9S12NE64 Data Sheet, Rev. 1.1 466 Freescale Semiconductor
Functional Description
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the behavior where the BDC is running in a frequency much greater than the CPU frequency. In this case, the command could time out before the data is ready to be retrieved. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDC and CPU) when the hardware handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and continue to be able to retrieve the data from an issued read command. However, as soon as the handshake pulse (ACK pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no longer available for retrieval. Any falling edge of the BKGD pin after the time-out period is considered to be a new command or a SYNC request. Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. The next falling edge of the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse.
17.4.13 Operation in Wait Mode
The BDM cannot be used in wait mode if the system disables the clocks to the BDM. There is a clearing mechanism associated with the WAIT instruction when the clocks to the BDM (CPU core platform) are disabled. As the clocks restart from wait mode, the BDM receives a soft reset (clearing any command in progress) and the ACK function will be disabled. This is a change from previous BDM modules.
17.4.14 Operation in Stop Mode
The BDM is completely shutdown in stop mode. There is a clearing mechanism associated with the STOP instruction. STOP must be enabled and the part must go into stop mode for this to occur. As the clocks restart from stop mode, the BDM receives a soft reset (clearing any command in progress) and the ACK function will be disabled. This is a change from previous BDM modules.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 467
Chapter 17 Background Debug Module (BDMV4)
MC9S12NE64 Data Sheet, Rev. 1.1 468 Freescale Semiconductor
Chapter 18 Debug Module (DBGV1)
18.1 Introduction
This section describes the functionality of the debug (DBG) sub-block of the HCS12 core platform. The DBG module is designed to be fully compatible with the existing BKP_HCS12_A module (BKP mode) and furthermore provides an on-chip trace buffer with flexible triggering capability (DBG mode). The DBG module provides for non-intrusive debug of application software. The DBG module is optimized for the HCS12 16-bit architecture.
18.1.1
Features
The DBG module in BKP mode includes these distinctive features: * Full or dual breakpoint mode -- Compare on address and data (full) -- Compare on either of two addresses (dual) * BDM or SWI breakpoint -- Enter BDM on breakpoint (BDM) -- Execute SWI on breakpoint (SWI) * Tagged or forced breakpoint -- Break just before a specific instruction will begin execution (TAG) -- Break on the first instruction boundary after a match occurs (Force) * Single, range, or page address compares -- Compare on address (single) -- Compare on address 256 byte (range) -- Compare on any 16K page (page) * At forced breakpoints compare address on read or write * High and/or low byte data compares * Comparator C can provide an additional tag or force breakpoint (enhancement for BKP mode)
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 469
Chapter 18 Debug Module (DBGV1)
The DBG in DBG mode includes these distinctive features: * Three comparators (A, B, and C) -- Dual mode, comparators A and B used to compare addresses -- Full mode, comparator A compares address and comparator B compares data -- Can be used as trigger and/or breakpoint -- Comparator C used in LOOP1 capture mode or as additional breakpoint * Four capture modes -- Normal mode, change-of-flow information is captured based on trigger specification -- Loop1 mode, comparator C is dynamically updated to prevent redundant change-of-flow storage. -- Detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer -- Profile mode, last instruction address executed by CPU is returned when trace buffer address is read * Two types of breakpoint or debug triggers -- Break just before a specific instruction will begin execution (tag) -- Break on the first instruction boundary after a match occurs (force) * BDM or SWI breakpoint -- Enter BDM on breakpoint (BDM) -- Execute SWI on breakpoint (SWI) * Nine trigger modes for comparators A and B --A -- A or B -- A then B -- A and B, where B is data (full mode) -- A and not B, where B is data (full mode) -- Event only B, store data -- A then event only B, store data -- Inside range, A  address  B -- Outside range, address <  or address > B * Comparator C provides an additional tag or force breakpoint when capture mode is not configured in LOOP1 mode. * Sixty-four word (16 bits wide) trace buffer for storing change-of-flow information, event only data and other bus information. -- Source address of taken conditional branches (long, short, bit-conditional, and loop constructs) -- Destination address of indexed JMP, JSR, and CALL instruction. -- Destination address of RTI, RTS, and RTC instructions -- Vector address of interrupts, except for SWI and BDM vectors
MC9S12NE64 Data Sheet, Rev. 1.1 470 Freescale Semiconductor
Introduction
-- -- -- --
Data associated with event B trigger modes Detail report mode stores address and data for all cycles except program (P) and free (f) cycles Current instruction address when in profiling mode BGND is not considered a change-of-flow (cof) by the debugger
18.1.2
Modes of Operation
There are two main modes of operation: breakpoint mode and debug mode. Each one is mutually exclusive of the other and selected via a software programmable control bit. In the breakpoint mode there are two sub-modes of operation: * Dual address mode, where a match on either of two addresses will cause the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). * Full breakpoint mode, where a match on address and data will cause the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). In debug mode, there are several sub-modes of operation. * Trigger modes There are many ways to create a logical trigger. The trigger can be used to capture bus information either starting from the trigger or ending at the trigger. Types of triggers (A and B are registers): -- A only -- A or B -- A then B -- Event only B (data capture) -- A then event only B (data capture) -- A and B, full mode -- A and not B, full mode -- Inside range -- Outside range * Capture modes There are several capture modes. These determine which bus information is saved and which is ignored. -- Normal: save change-of-flow program fetches -- Loop1: save change-of-flow program fetches, ignoring duplicates -- Detail: save all bus operations except program and free cycles -- Profile: poll target from external device
18.1.3
Block Diagram
Figure 18-1 is a block diagram of this module in breakpoint mode. Figure 18-2 is a block diagram of this module in debug mode.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 471
Chapter 18 Debug Module (DBGV1) CLOCKS AND CONTROL SIGNALS CONTROL BLOCK BREAKPOINT MODES AND GENERATION OF SWI, FORCE BDM, AND TAGS CONTROL SIGNALS RESULTS SIGNALS CONTROL BITS READ/WRITE CONTROL BKP CONTROL SIGNALS
......
......
EXPANSION ADDRESS ADDRESS WRITE DATA READ DATA
REGISTER BLOCK BKPCT0
BKPCT1 COMPARE BLOCK BKP READ DATA BUS WRITE DATA BUS BKP0X COMPARATOR EXPANSION ADDRESSES
BKP0H
COMPARATOR
ADDRESS HIGH
ADDRESS LOW BKP0L COMPARATOR EXPANSION ADDRESSES BKP1X COMPARATOR DATA HIGH BKP1H COMPARATOR DATA/ADDRESS HIGH MUX DATA/ADDRESS LOW MUX READ DATA HIGH COMPARATOR READ DATA LOW COMPARATOR ADDRESS HIGH DATA LOW ADDRESS LOW
BKP1L
COMPARATOR
Figure 18-1. DBG Block Diagram in BKP Mode
MC9S12NE64 Data Sheet, Rev. 1.1 472 Freescale Semiconductor
External Signal Description
DBG READ DATA BUS ADDRESS BUS CONTROL WRITE DATA BUS READ DATA BUS READ/WRITE DBG MODE ENABLE CHANGE-OF-FLOW INDICATORS MCU IN BDM DETAIL EVENT ONLY CPU PROGRAM COUNTER STORE POINTER INSTRUCTION LAST CYCLE REGISTER BUS CLOCK M U X 64 x 16 BIT WORD TRACE BUFFER PROFILE CAPTURE MODE TRACE BUFFER OR PROFILING DATA ADDRESS/DATA/CONTROL REGISTERS COMPARATOR A COMPARATOR B COMPARATOR C CONTROL MATCH_A MATCH_B MATCH_C LOOP1 TRACER BUFFER CONTROL LOGIC
TAG FORCE
M U X
WRITE DATA BUS READ DATA BUS
M U X
M U X
LAST INSTRUCTION ADDRESS
PROFILE CAPTURE REGISTER
READ/WRITE
Figure 18-2. DBG Block Diagram in DBG Mode
18.2
External Signal Description
The DBG sub-module relies on the external bus interface (generally the MEBI) when the DBG is matching on the external bus. The tag pins in Table 18-1 (part of the MEBI) may also be a part of the breakpoint operation.
Table 18-1. External System Pins Associated with DBG and MEBI
Pin Name BKGD/MODC/ TAGHI PE3/LSTRB/ TAGLO Pin Functions TAGHI TAGLO Description When instruction tagging is on, a 0 at the falling edge of E tags the high half of the instruction word being read into the instruction queue. In expanded wide mode or emulation narrow modes, when instruction tagging is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of the instruction word being read into the instruction queue.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 473
Chapter 18 Debug Module (DBGV1)
18.3
Memory Map and Register Definition
A summary of the registers associated with the DBG sub-block is shown in Figure 18-3. Detailed descriptions of the registers and bits are given in the subsections that follow.
18.3.1
Module Memory Map
Table 18-2. DBGV1 Memory Map
Address Offset Debug Control Register (DBGC1) Debug Status and Control Register (DBGSC) Debug Trace Buffer Register High (DBGTBH) Debug Trace Buffer Register Low (DBGTBL) 4 5 6 8 9 A B Debug Count Register (DBGCNT) Debug Comparator C Extended Register (DBGCCX) Debug Comparator C Register High (DBGCCH) Debug Comparator C Register Low (DBGCCL) Debug Control Register 2 (DBGC2) / (BKPCT0) Debug Control Register 3 (DBGC3) / (BKPCT1) Debug Comparator A Extended Register (DBGCAX) / (/BKP0X) Debug Comparator A Register High (DBGCAH) / (BKP0H) Debug Comparator A Register Low (DBGCAL) / (BKP0L) Debug Comparator B Extended Register (DBGCBX) / (BKP1X) E F Debug Comparator B Register High (DBGCBH) / (BKP1H) Debug Comparator B Register Low (DBGCBL) / (BKP1L) Use Access R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
18.3.2
Register Descriptions
This section consists of the DBG register descriptions in address order. Most of the register bits can be written to in either BKP or DBG mode, although they may not have any effect in one of the modes. However, the only bits in the DBG module that can be written while the debugger is armed (ARM = 1) are DBGEN and ARM
Name1 DBGC1 R W R W = Unimplemented or Reserved Bit 7 DBGEN AF 6 ARM BF 5 TRGSEL CF 4 BEGIN 0 3 DBGBRK 2 0 1 Bit 0 CAPMOD
DBGSC
TRG
Figure 18-3. DBG Register Summary
MC9S12NE64 Data Sheet, Rev. 1.1 474 Freescale Semiconductor
Memory Map and Register Definition
Name1 DBGTBH R W R W R W R W R W R W R W R W R W R W R W R W R W R W
Bit 7 Bit 15
6 Bit 14
5 Bit 13
4 Bit 12
3 Bit 11
2 Bit 10
1 Bit 9
Bit 0 Bit 8
DBGTBL
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DBGCNT
TBF
0
CNT
DBGCCX(2)
PAGSEL
EXTCMP
DBGCCH(2)
Bit 15
14
13
12
11
10
9
Bit 8
DBGCCL(2)
Bit 7
6
5
4
3
2
1
Bit 0
DBGC2 BKPCT0 DBGC3 BKPCT1 DBGCAX BKP0X DBGCAH BKP0H DBGCAL BKP0L DBGCBX BKP1X DBGCBH BKP1H DBGCBL BKP1L
BKABEN
FULL
BDM
TAGAB
BKCEN
TAGC
RWCEN
RWC
BKAMBH
BKAMBL
BKBMBH
BKBMBL
RWAEN
RWA
RWBEN
RWB
PAGSEL
EXTCMP
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
PAGSEL
EXTCMP
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved
Figure 18-3. DBG Register Summary (continued)
1
The DBG module is designed for backwards compatibility to existing BKP modules. Register and bit names have changed from the BKP module. This column shows the DBG register name, as well as the BKP register name for reference. 2 Comparator C can be used to enhance the BKP mode by providing a third breakpoint.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 475
Chapter 18 Debug Module (DBGV1)
18.3.2.1
Debug Control Register 1 (DBGC1)
NOTE All bits are used in DBG mode only.
7 6 5 4 3 2 1 0
R DBGEN W Reset 0 0 0 0 0 ARM TRGSEL BEGIN DBGBRK
0 CAPMOD 0 0 0
= Unimplemented or Reserved
Figure 18-4. Debug Control Register (DBGC1)
NOTE This register cannot be written if BKP mode is enabled (BKABEN in DBGC2 is set).
Table 18-3. DBGC1 Field Descriptions
Field 7 DBGEN Description DBG Mode Enable Bit -- The DBGEN bit enables the DBG module for use in DBG mode. This bit cannot be set if the MCU is in secure mode. 0 DBG mode disabled 1 DBG mode enabled Arm Bit -- The ARM bit controls whether the debugger is comparing and storing data in the trace buffer. See Section 18.4.2.4, "Arming the DBG Module," for more information. 0 Debugger unarmed 1 Debugger armed Note: This bit cannot be set if the DBGEN bit is not also being set at the same time. For example, a write of 01 to DBGEN[7:6] will be interpreted as a write of 00. Trigger Selection Bit -- The TRGSEL bit controls the triggering condition for comparators A and B in DBG mode. It serves essentially the same function as the TAGAB bit in the DBGC2 register does in BKP mode. See Section 18.4.2.1.2, "Trigger Selection," for more information. TRGSEL may also determine the type of breakpoint based on comparator A and B if enabled in DBG mode (DBGBRK = 1). Please refer to Section 18.4.3.1, "Breakpoint Based on Comparator A and B." 0 Trigger on any compare address match 1 Trigger before opcode at compare address gets executed (tagged-type) Begin/End Trigger Bit -- The BEGIN bit controls whether the trigger begins or ends storing of data in the trace buffer. See Section 18.4.2.8.1, "Storing with Begin-Trigger," and Section 18.4.2.8.2, "Storing with End-Trigger," for more details. 0 Trigger at end of stored data 1 Trigger before storing data
6 ARM
5 TRGSEL
4 BEGIN
MC9S12NE64 Data Sheet, Rev. 1.1 476 Freescale Semiconductor
Memory Map and Register Definition
Table 18-3. DBGC1 Field Descriptions (continued)
Field 3 DBGBRK Description DBG Breakpoint Enable Bit -- The DBGBRK bit controls whether the debugger will request a breakpoint based on comparator A and B to the CPU upon completion of a tracing session. Please refer to Section 18.4.3, "Breakpoints," for further details. 0 CPU break request not enabled 1 CPU break request enabled Capture Mode Field -- See Table 18-4 for capture mode field definitions. In LOOP1 mode, the debugger will automatically inhibit redundant entries into capture memory. In detail mode, the debugger is storing address and data for all cycles except program fetch (P) and free (f) cycles. In profile mode, the debugger is returning the address of the last instruction executed by the CPU on each access of trace buffer address. Refer to Section 18.4.2.6, "Capture Modes," for more information.
1:0 CAPMOD
Table 18-4. CAPMOD Encoding
CAPMOD 00 01 10 11 Description Normal LOOP1 DETAIL PROFILE
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 477
Chapter 18 Debug Module (DBGV1)
18.3.2.2
Debug Status and Control Register (DBGSC)
7 6 5 4 3 2 1 0
R W Reset
AF
BF
CF
0 TRG
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-5. Debug Status and Control Register (DBGSC) Table 18-5. DBGSC Field Descriptions
Field 7 AF Description Trigger A Match Flag -- The AF bit indicates if trigger A match condition was met since arming. This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register. 0 Trigger A did not match 1 Trigger A match Trigger B Match Flag -- The BF bit indicates if trigger B match condition was met since arming.This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register. 0 Trigger B did not match 1 Trigger B match Comparator C Match Flag -- The CF bit indicates if comparator C match condition was met since arming.This bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register. 0 Comparator C did not match 1 Comparator C match Trigger Mode Bits -- The TRG bits select the trigger mode of the DBG module as shown Table 18-6. See Section 18.4.2.5, "Trigger Modes," for more detail.
6 BF
5 CF
3:0 TRG
Table 18-6. Trigger Mode Encoding
TRG Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001  1111 Meaning A only A or B A then B Event only B A then event only B A and B (full mode) A and Not B (full mode) Inside range Outside range Reserved (Defaults to A only)
MC9S12NE64 Data Sheet, Rev. 1.1 478 Freescale Semiconductor
Memory Map and Register Definition
18.3.2.3
Debug Trace Buffer Register (DBGTB)
15 14 13 12 11 10 9 8
R W Reset
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
Figure 18-6. Debug Trace Buffer Register High (DBGTBH)
7 6 5 4 3 2 1 0
R W Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
u
u
u
u
u
u
u
u
= Unimplemented or Reserved
Figure 18-7. Debug Trace Buffer Register Low (DBGTBL) Table 18-7. DBGTB Field Descriptions
Field 15:0 Description Trace Buffer Data Bits -- The trace buffer data bits contain the data of the trace buffer. This register can be read only as a word read. Any byte reads or misaligned access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace buffer address. The same is true for word reads while the debugger is armed. In addition, this register may appear to contain incorrect data if it is not read with the same capture mode bit settings as when the trace buffer data was recorded (See Section 18.4.2.9, "Reading Data from Trace Buffer"). Because reads will reflect the contents of the trace buffer RAM, the reset state is undefined.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 479
Chapter 18 Debug Module (DBGV1)
18.3.2.4
Debug Count Register (DBGCNT)
7 6 5 4 3 2 1 0
R W Reset
TBF
0
CNT
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-8. Debug Count Register (DBGCNT) Table 18-8. DBGCNT Field Descriptions
Field 7 TBF 5:0 CNT Description Trace Buffer Full -- The TBF bit indicates that the trace buffer has stored 64 or more words of data since it was last armed. If this bit is set, then all 64 words will be valid data, regardless of the value in CNT[5:0]. The TBF bit is cleared when ARM in DBGC1 is written to a 1. Count Value -- The CNT bits indicate the number of valid data words stored in the trace buffer. Table 18-9 shows the correlation between the CNT bits and the number of valid data words in the trace buffer. When the CNT rolls over to 0, the TBF bit will be set and incrementing of CNT will continue if DBG is in end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a 1.
Table 18-9. CNT Decoding Table
TBF 0 0 0 CNT 000000 000001 000010 .. .. 111110 111111 000000 Description No data valid 1 word valid 2 words valid .. .. 62 words valid 63 words valid 64 words valid; if BEGIN = 1, the ARM bit will be cleared. A breakpoint will be generated if DBGBRK = 1 64 words valid, oldest data has been overwritten by most recent data
0 1
1
000001 .. .. 111111
MC9S12NE64 Data Sheet, Rev. 1.1 480 Freescale Semiconductor
Memory Map and Register Definition
18.3.2.5
Debug Comparator C Extended Register (DBGCCX)
7 6 5 4 3 2 1 0
R PAGSEL W Reset 0 0 0 0 0 0 0 0 EXTCMP
Figure 18-9. Debug Comparator C Extended Register (DBGCCX) Table 18-10. DBGCCX Field Descriptions
Field 7:6 PAGSEL Description Page Selector Field -- In both BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 18-11. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01, respectively). Comparator C Extended Compare Bits -- The EXTCMP bits are used as comparison address bits as shown in Table 18-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Note: Comparator C can be used when the DBG module is configured for BKP mode. Extended addressing comparisons for comparator C use PAGSEL and will operate differently to the way that comparator A and B operate in BKP mode.
5:0 EXTCMP
Table 18-11. PAGSEL Decoding1
PAGSEL 00 01 103 112
1 2
Description Normal (64k) PPAGE (256 -- 16K pages) DPAGE (reserved) (256 -- 4K pages) EPAGE (reserved) (256 -- 1K pages)
EXTCMP Not used EXTCMP[5:0] is compared to address bits [21:16]2 EXTCMP[3:0] is compared to address bits [19:16] EXTCMP[1:0] is compared to address bits [17:16]
Comment No paged memory PPAGE[7:0] / XAB[21:14] becomes address bits [21:14]1 DPAGE / XAB[21:14] becomes address bits [19:12] EPAGE / XAB[21:14] becomes address bits [17:10]
See Figure 18-10. Current HCS12 implementations have PPAGE limited to 6 bits. Therefore, EXTCMP[5:4] should be set to 00. 3 Data page (DPAGE) and Extra page (EPAGE) are reserved for implementation on devices that support paged data and extra space.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 481
Chapter 18 Debug Module (DBGV1)
DBGCXX PAGSEL 7 6 0 5 0 4 3 EXTCMP 2 1 BIT 0 BIT 15
DBGCXH[15:12] BIT 14 BIT 13 BIT 12 BKP/DBG MODE
9 8
SEE NOTE 1 PORTK/XAB XAB21 XAB20 XAB19 XAB18 XAB17 XAB16 XAB15 XAB14
PPAGE
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
SEE NOTE 2 NOTES: 1. In BKP and DBG mode, PAGSEL selects the type of paging as shown in Table 18-11. 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0]. Therefore, EXTCMP[5:4] = 00.
Figure 18-10. Comparator C Extended Comparison in BKP/DBG Mode
18.3.2.6
Debug Comparator C Register (DBGCC)
15 14 13 12 11 10
R W Reset
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-11. Debug Comparator C Register High (DBGCCH)
7 6 5 4 3 2 1 0
R W Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-12. Debug Comparator C Register Low (DBGCCL) Table 18-12. DBGCC Field Descriptions
Field 15:0 Description Comparator C Compare Bits -- The comparator C compare bits control whether comparator C will compare the address bus bits [15:0] to a logic 1 or logic 0. See Table 18-13. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1 Note: This register will be cleared automatically when the DBG module is armed in LOOP1 mode.
MC9S12NE64 Data Sheet, Rev. 1.1 482 Freescale Semiconductor
Memory Map and Register Definition
Table 18-13. Comparator C Compares
PAGSEL x0 x1 EXTCMP Compare No compare EXTCMP[5:0] = XAB[21:16] High-Byte Compare DBGCCH[7:0] = AB[15:8] DBGCCH[7:0] = XAB[15:14],AB[13:8]
18.3.2.7
Debug Control Register 2 (DBGC2)
7 6 5 4 3 2 1 0
R W Reset
1
BKABEN1 0
FULL 0
BDM 0
TAGAB 0
BKCEN2 0
TAGC2 0
RWCEN2 0
RWC2 0
When BKABEN is set (BKP mode), all bits in DBGC2 are available. When BKABEN is cleared and DBG is used in DBG mode, bits FULL and TAGAB have no meaning. 2 These bits can be used in BKP mode and DBG mode (when capture mode is not set in LOOP1) to provide a third breakpoint.
Figure 18-13. Debug Control Register 2 (DBGC2) Table 18-14. DBGC2 Field Descriptions
Field 7 BKABEN Description Breakpoint Using Comparator A and B Enable -- This bit enables the breakpoint capability using comparator A and B, when set (BKP mode) the DBGEN bit in DBGC1 cannot be set. 0 Breakpoint module off 1 Breakpoint module on Full Breakpoint Mode Enable -- This bit controls whether the breakpoint module is in dual mode or full mode. In full mode, comparator A is used to match address and comparator B is used to match data. See Section 18.4.1.2, "Full Breakpoint Mode," for more details. 0 Dual address mode enabled 1 Full breakpoint mode enabled Background Debug Mode Enable -- This bit determines if the breakpoint causes the system to enter background debug mode (BDM) or initiate a software interrupt (SWI). 0 Go to software interrupt on a break request 1 Go to BDM on a break request Comparator A/B Tag Select -- This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint. 0 On match, break at the next instruction boundary (force) 1 On match, break if/when the instruction is about to be executed (tagged) Breakpoint Comparator C Enable Bit -- This bit enables the breakpoint capability using comparator C. 0 Comparator C disabled for breakpoint 1 Comparator C enabled for breakpoint Note: This bit will be cleared automatically when the DBG module is armed in loop1 mode. Comparator C Tag Select -- This bit controls whether the breakpoint will cause a break on the next instruction boundary (force) or on a match that will be an executable opcode (tagged). Non-executed opcodes cannot cause a tagged breakpoint. 0 On match, break at the next instruction boundary (force) 1 On match, break if/when the instruction is about to be executed (tagged)
6 FULL
5 BDM
4 TAGAB
3 BKCEN
2 TAGC
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 483
Chapter 18 Debug Module (DBGV1)
Table 18-14. DBGC2 Field Descriptions (continued)
Field 1 RWCEN Description Read/Write Comparator C Enable Bit -- The RWCEN bit controls whether read or write comparison is enabled for comparator C. RWCEN is not useful for tagged breakpoints. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Read/Write Comparator C Value Bit -- The RWC bit controls whether read or write is used in compare for comparator C. The RWC bit is not used if RWCEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched
0 RWC
18.3.2.8
Debug Control Register 3 (DBGC3)
7 6 5 4 3 2 1 0
R W Reset
1 2
BKAMBH1 0
BKAMBL1 0
BKBMBH2 0
BKBMBL2 0
RWAEN 0
RWA 0
RWBEN 0
RWB 0
In DBG mode, BKAMBH:BKAMBL has no meaning and are forced to 0's. In DBG mode, BKBMBH:BKBMBL are used in full mode to qualify data.
Figure 18-14. Debug Control Register 3 (DBGC3) Table 18-15. DBGC3 Field Descriptions
Field Description
7:6 Breakpoint Mask High Byte for First Address -- In dual or full mode, these bits may be used to mask (disable) BKAMB[H:L] the comparison of the high and/or low bytes of the first address breakpoint. The functionality is as given in Table 18-16. The x:0 case is for a full address compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {DBGCAX[5:0], DBGCAH[5:0], DBGCAL[7:0]}, where DBGAX[5:0] corresponds to PPAGE[5:0] or extended address bits [19:14] and CPU address [13:0]. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {DBGCAH[7:0], DBGCAL[7:0]} which corresponds to CPU address [15:0]. Note: This extended address compare scheme causes an aliasing problem in BKP mode in which several physical addresses may match with a single logical address. This problem may be avoided by using DBG mode to generate breakpoints. The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BKAMBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if DBGCAX compares.
MC9S12NE64 Data Sheet, Rev. 1.1 484 Freescale Semiconductor
Memory Map and Register Definition
Table 18-15. DBGC3 Field Descriptions (continued)
Field Description
5:4 Breakpoint Mask High Byte and Low Byte of Data (Second Address) -- In dual mode, these bits may be BKBMB[H:L] used to mask (disable) the comparison of the high and/or low bytes of the second address breakpoint. The functionality is as given in Table 18-17. The x:0 case is for a full address compare. When a program page is selected, the full address compare will be based on bits for a 20-bit compare. The registers used for the compare are {DBGCBX[5:0], DBGCBH[5:0], DBGCBL[7:0]} where DBGCBX[5:0] corresponds to PPAGE[5:0] or extended address bits [19:14] and CPU address [13:0]. When a program page is not selected, the full address compare will be based on bits for a 16-bit compare. The registers used for the compare are {DBGCBH[7:0], DBGCBL[7:0]} which corresponds to CPU address [15:0]. Note: This extended address compare scheme causes an aliasing problem in BKP mode in which several physical addresses may match with a single logical address. This problem may be avoided by using DBG mode to generate breakpoints. The 1:0 case is not sensible because it would ignore the high order address and compare the low order and expansion addresses. Logic forces this case to compare all address lines (effectively ignoring the BKBMBH control bit). The 1:1 case is useful for triggering a breakpoint on any access to a particular expansion page. This only makes sense if a program page is being accessed so that the breakpoint trigger will occur only if DBGCBX compares. In full mode, these bits may be used to mask (disable) the comparison of the high and/or low bytes of the data breakpoint. The functionality is as given in Table 18-18. 3 RWAEN Read/Write Comparator A Enable Bit -- The RWAEN bit controls whether read or write comparison is enabled for comparator A. See Section 18.4.2.1.1, "Read or Write Comparison," for more information. This bit is not useful for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Read/Write Comparator A Value Bit -- The RWA bit controls whether read or write is used in compare for comparator A. The RWA bit is not used if RWAEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched Read/Write Comparator B Enable Bit -- The RWBEN bit controls whether read or write comparison is enabled for comparator B. See Section 18.4.2.1.1, "Read or Write Comparison," for more information. This bit is not useful for tagged operations. 0 Read/Write is not used in comparison 1 Read/Write is used in comparison Read/Write Comparator B Value Bit -- The RWB bit controls whether read or write is used in compare for comparator B. The RWB bit is not used if RWBEN = 0. 0 Write cycle will be matched 1 Read cycle will be matched Note: RWB and RWBEN are not used in full mode.
2 RWA
1 RWBEN
0 RWB
Table 18-16. Breakpoint Mask Bits for First Address
BKAMBH:BKAMBL x:0 0:1 1:1
1
Address Compare Full address compare 256 byte address range 16K byte address range
DBGCAX Yes1 Yes1 Yes
1
DBGCAH Yes Yes No
DBGCAL Yes No No
If PPAGE is selected.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 485
Chapter 18 Debug Module (DBGV1)
Table 18-17. Breakpoint Mask Bits for Second Address (Dual Mode)
BKBMBH:BKBMBL x:0 0:1 1:1
1
Address Compare Full address compare 256 byte address range 16K byte address range
DBGCBX Yes
1
DBGCBH Yes Yes No
DBGCBL Yes No No
Yes1 Yes1
If PPAGE is selected.
Table 18-18. Breakpoint Mask Bits for Data Breakpoints (Full Mode)
BKBMBH:BKBMBL 0:0 0:1 1:0 1:1
1
Data Compare High and low byte compare High byte Low byte No compare
DBGCBX No No
1 1
DBGCBH Yes Yes No No
DBGCBL Yes No Yes No
No1 No1
Expansion addresses for breakpoint B are not applicable in this mode.
MC9S12NE64 Data Sheet, Rev. 1.1 486 Freescale Semiconductor
Memory Map and Register Definition
18.3.2.9
Debug Comparator A Extended Register (DBGCAX)
7 6 5 4 3 2 1 0
R PAGSEL W Reset 0 0 0 0 0 0 0 0 EXTCMP
Figure 18-15. Debug Comparator A Extended Register (DBGCAX) Table 18-19. DBGCAX Field Descriptions
Field 7:6 PAGSEL Description Page Selector Field -- If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 18-20. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01, respectively). In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address is in the FLASH/ROM memory space. 5:0 EXTCMP Comparator A Extended Compare Bits -- The EXTCMP bits are used as comparison address bits as shown in Table 18-20 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core.
Table 18-20. Comparator A or B Compares
Mode BKP
1
EXTCMP Compare No compare EXTCMP[5:0] = XAB[19:14] No compare EXTCMP[5:0] = XAB[21:16]
High-Byte Compare DBGCxH[7:0] = AB[15:8] DBGCxH[5:0] = AB[13:8] DBGCxH[7:0] = AB[15:8] DBGCxH[7:0] = XAB[15:14], AB[13:8]
Not FLASH/ROM access FLASH/ROM access PAGSEL = 00 PAGSEL = 01
DBG2
1 2
See Figure 18-16. See Figure 18-10 (note that while this figure provides extended comparisons for comparator C, the figure also pertains to comparators A and B in DBG mode only).
PAGSEL DBGCXX 0 0 5 4 EXTCMP 3 2 1 BIT 0
PORTK/XAB
XAB21
XAB20
XAB19
XAB18
XAB17
XAB16
XAB15
XAB14
PPAGE
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
SEE NOTE 2 NOTES: 1. In BKP mode, PAGSEL has no functionality. Therefore, set PAGSEL to 00 (reset state). 2. Current HCS12 implementations are limited to six PPAGE bits, PIX[5:0].
Figure 18-16. Comparators A and B Extended Comparison in BKP Mode
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 487
BKP MODE
SEE NOTE 1
Chapter 18 Debug Module (DBGV1)
18.3.2.10 Debug Comparator A Register (DBGCA)
15 14 13 12 11 10 9 8
R Bit 15 W Reset 0 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Figure 18-17. Debug Comparator A Register High (DBGCAH)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 18-18. Debug Comparator A Register Low (DBGCAL) Table 18-21. DBGCA Field Descriptions
Field 15:0 15:0 Description Comparator A Compare Bits -- The comparator A compare bits control whether comparator A compares the address bus bits [15:0] to a logic 1 or logic 0. See Table 18-20. 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit to a logic 1
18.3.2.11 Debug Comparator B Extended Register (DBGCBX)
7 6 5 4 3 2 1 0
R PAGSEL W Reset 0 0 0 0 0 0 0 0 EXTCMP
Figure 18-19. Debug Comparator B Extended Register (DBGCBX) Table 18-22. DBGCBX Field Descriptions
Field 7:6 PAGSEL Description Page Selector Field -- If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in Table 18-11. DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and 11 will be interpreted as values of 00 and 01, respectively.) In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address is in the FLASH/ROM memory space. 5:0 EXTCMP Comparator B Extended Compare Bits -- The EXTCMP bits are used as comparison address bits as shown in Table 18-11 along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see Table 18-20.
MC9S12NE64 Data Sheet, Rev. 1.1 488 Freescale Semiconductor
Functional Description
18.3.2.12 Debug Comparator B Register (DBGCB)
15 14 13 12 11 10 9 8
R Bit 15 W Reset 0 0 0 0 0 0 0 0 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Figure 18-20. Debug Comparator B Register High (DBGCBH)
7 6 5 4 3 2 1 0
R Bit 7 W Reset 0 0 0 0 0 0 0 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Figure 18-21. Debug Comparator B Register Low (DBGCBL) Table 18-23. DBGCB Field Descriptions
Field 15:0 15:0 Description Comparator B Compare Bits -- The comparator B compare bits control whether comparator B compares the address bus bits [15:0] or data bus bits [15:0] to a logic 1 or logic 0. See Table 18-20. 0 Compare corresponding address bit to a logic 0, compares to data if in Full mode 1 Compare corresponding address bit to a logic 1, compares to data if in Full mode
18.4
Functional Description
This section provides a complete functional description of the DBG module. The DBG module can be configured to run in either of two modes, BKP or DBG. BKP mode is enabled by setting BKABEN in DBGC2. DBG mode is enabled by setting DBGEN in DBGC1. Setting BKABEN in DBGC2 overrides the DBGEN in DBGC1 and prevents DBG mode. If the part is in secure mode, DBG mode cannot be enabled.
18.4.1
DBG Operating in BKP Mode
In BKP mode, the DBG will be fully backwards compatible with the existing BKP_ST12_A module. The DBGC2 register has four additional bits that were not available on existing BKP_ST12_A modules. As long as these bits are written to either all 1s or all 0s, they should be transparent to the user. All 1s would enable comparator C to be used as a breakpoint, but tagging would be enabled. The match address register would be all 0s if not modified by the user. Therefore, code executing at address 0x0000 would have to occur before a breakpoint based on comparator C would happen. The DBG module in BKP mode supports two modes of operation: dual address mode and full breakpoint mode. Within each of these modes, forced or tagged breakpoint types can be used. Forced breakpoints occur at the next instruction boundary if a match occurs and tagged breakpoints allow for breaking just before the tagged instruction executes. The action taken upon a successful match can be to either place the CPU in background debug mode or to initiate a software interrupt.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 489
Chapter 18 Debug Module (DBGV1)
The breakpoint can operate in dual address mode or full breakpoint mode. Each of these modes is discussed in the subsections below.
18.4.1.1
Dual Address Mode
When dual address mode is enabled, two address breakpoints can be set. Each breakpoint can cause the system to enter background debug mode or to initiate a software interrupt based upon the state of BDM in DBGC2 being logic 1 or logic 0, respectively. BDM requests have a higher priority than SWI requests. No data breakpoints are allowed in this mode. TAGAB in DBGC2 selects whether the breakpoint mode is forced or tagged. The BKxMBH:L bits in DBGC3 select whether or not the breakpoint is matched exactly or is a range breakpoint. They also select whether the address is matched on the high byte, low byte, both bytes, and/or memory expansion. The RWx and RWxEN bits in DBGC3 select whether the type of bus cycle to match is a read, write, or read/write when performing forced breakpoints.
18.4.1.2
Full Breakpoint Mode
Full breakpoint mode requires a match on address and data for a breakpoint to occur. Upon a successful match, the system will enter background debug mode or initiate a software interrupt based upon the state of BDM in DBGC2 being logic 1 or logic 0, respectively. BDM requests have a higher priority than SWI requests. R/W matches are also allowed in this mode. TAGAB in DBGC2 selects whether the breakpoint mode is forced or tagged. When TAGAB is set in DBGC2, only addresses are compared and data is ignored. The BKAMBH:L bits in DBGC3 select whether or not the breakpoint is matched exactly, is a range breakpoint, or is in page space. The BKBMBH:L bits in DBGC3 select whether the data is matched on the high byte, low byte, or both bytes. RWA and RWAEN bits in DBGC2 select whether the type of bus cycle to match is a read or a write when performing forced breakpoints. RWB and RWBEN bits in DBGC2 are not used in full breakpoint mode. NOTE The full trigger mode is designed to be used for either a word access or a byte access, but not both at the same time. Confusing trigger operation (seemingly false triggers or no trigger) can occur if the trigger address occurs in the user program as both byte and word accesses.
18.4.1.3
Breakpoint Priority
Breakpoint operation is first determined by the state of the BDM module. If the BDM module is already active, meaning the CPU is executing out of BDM firmware, breakpoints are not allowed. In addition, while executing a BDM TRACE command, tagging into BDM is not allowed. If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests. This condition applies to both forced and tagged breakpoints. In all cases, BDM related breakpoints will have priority over those generated by the Breakpoint sub-block. This priority includes breakpoints enabled by the TAGLO and TAGHI external pins of the system that interface with the BDM directly and whose signal information passes through and is used by the breakpoint sub-block.
MC9S12NE64 Data Sheet, Rev. 1.1 490 Freescale Semiconductor
Functional Description
NOTE BDM should not be entered from a breakpoint unless the ENABLE bit is set in the BDM. Even if the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If the BDM is not serviced by the monitor then the breakpoint would be re-asserted when the BDM returns to normal CPU flow. There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled. When program control returns from a tagged breakpoint through an RTI or a BDM GO command, it will return to the instruction whose tag generated the breakpoint. Unless breakpoints are disabled or modified in the service routine or active BDM session, the instruction will be tagged again and the breakpoint will be repeated. In the case of BDM breakpoints, this situation can also be avoided by executing a TRACE1 command before the GO to increment the program flow past the tagged instruction.
18.4.1.4
Using Comparator C in BKP Mode
The original BKP_ST12_A module supports two breakpoints. The DBG_ST12_A module can be used in BKP mode and allow a third breakpoint using comparator C. Four additional bits, BKCEN, TAGC, RWCEN, and RWC in DBGC2 in conjunction with additional comparator C address registers, DBGCCX, DBGCCH, and DBGCCL allow the user to set up a third breakpoint. Using PAGSEL in DBGCCX for expanded memory will work differently than the way paged memory is done using comparator A and B in BKP mode. See Section 18.3.2.5, "Debug Comparator C Extended Register (DBGCCX)," for more information on using comparator C.
18.4.2
DBG Operating in DBG Mode
Enabling the DBG module in DBG mode, allows the arming, triggering, and storing of data in the trace buffer and can be used to cause CPU breakpoints. The DBG module is made up of three main blocks, the comparators, trace buffer control logic, and the trace buffer. NOTE In general, there is a latency between the triggering event appearing on the bus and being detected by the DBG circuitry. In general, tagged triggers will be more predictable than forced triggers.
18.4.2.1
Comparators
The DBG contains three comparators, A, B, and C. Comparator A compares the core address bus with the address stored in DBGCAH and DBGCAL. Comparator B compares the core address bus with the address stored in DBGCBH and DBGCBL except in full mode, where it compares the data buses to the data stored in DBGCBH and DBGCBL. Comparator C can be used as a breakpoint generator or as the address comparison unit in the loop1 mode. Matches on comparator A, B, and C are signaled to the trace buffer
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 491
Chapter 18 Debug Module (DBGV1)
control (TBC) block. When PAGSEL = 01, registers DBGCAX, DBGCBX, and DBGCCX are used to match the upper addresses as shown in Table 18-11. NOTE If a tagged-type C breakpoint is set at the same address as an A/B tagged-type trigger (including the initial entry in an inside or outside range trigger), the C breakpoint will have priority and the trigger will not be recognized. 18.4.2.1.1 Read or Write Comparison
Read or write comparisons are useful only with TRGSEL = 0, because only opcodes should be tagged as they are "read" from memory. RWAEN and RWBEN are ignored when TRGSEL = 1. In full modes ("A and B" and "A and not B") RWAEN and RWA are used to select read or write comparisons for both comparators A and B. Table 18-24 shows the effect for RWAEN, RWA, and RW on the DBGCB comparison conditions. The RWBEN and RWB bits are not used and are ignored in full modes.
Table 18-24. Read or Write Comparison Logic Table
RWAEN bit 0 0 1 1 1 1 RWA bit x x 0 0 1 1 RW signal 0 1 0 1 0 1 Comment Write data bus Read data bus Write data bus No data bus compare since RW=1 No data bus compare since RW=0 Read data bus
18.4.2.1.2
Trigger Selection
The TRGSEL bit in DBGC1 is used to determine the triggering condition in DBG mode. TRGSEL applies to both trigger A and B except in the event only trigger modes. By setting TRGSEL, the comparators A and B will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged instruction executes (tagged-type trigger). With the TRGSEL bit cleared, a comparator match forces a trigger when the matching condition occurs (force-type trigger). NOTE If the TRGSEL is set, the address stored in the comparator match address registers must be an opcode address for the trigger to occur.
18.4.2.2
Trace Buffer Control (TBC)
The TBC is the main controller for the DBG module. Its function is to decide whether data should be stored in the trace buffer based on the trigger mode and the match signals from the comparator. The TBC also determines whether a request to break the CPU should occur.
MC9S12NE64 Data Sheet, Rev. 1.1 492 Freescale Semiconductor
Functional Description
18.4.2.3
Begin- and End-Trigger
The definitions of begin- and end-trigger as used in the DBG module are as follows: * Begin-trigger: Storage in trace buffer occurs after the trigger and continues until 64 locations are filled. * End-trigger: Storage in trace buffer occurs until the trigger, with the least recent data falling out of the trace buffer if more than 64 words are collected.
18.4.2.4
Arming the DBG Module
In DBG mode, arming occurs by setting DBGEN and ARM in DBGC1. The ARM bit in DBGC1 is cleared when the trigger condition is met in end-trigger mode or when the Trace Buffer is filled in begin-trigger mode. The TBC logic determines whether a trigger condition has been met based on the trigger mode and the trigger selection.
18.4.2.5
Trigger Modes
The DBG module supports nine trigger modes. The trigger modes are encoded as shown in Table 18-6. The trigger mode is used as a qualifier for either starting or ending the storing of data in the trace buffer. When the match condition is met, the appropriate flag A or B is set in DBGSC. Arming the DBG module clears the A, B, and C flags in DBGSC. In all trigger modes except for the event-only modes and DETAIL capture mode, change-of-flow addresses are stored in the trace buffer. In the event-only modes only the value on the data bus at the trigger event B will be stored. In DETAIL capture mode address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer. 18.4.2.5.1 A Only
In the A only trigger mode, if the match condition for A is met, the A flag in DBGSC is set and a trigger occurs. 18.4.2.5.2 A or B
In the A or B trigger mode, if the match condition for A or B is met, the corresponding flag in DBGSC is set and a trigger occurs. 18.4.2.5.3 A then B
In the A then B trigger mode, the match condition for A must be met before the match condition for B is compared. When the match condition for A or B is met, the corresponding flag in DBGSC is set. The trigger occurs only after A then B have matched. NOTE When tagging and using A then B, if addresses A and B are close together, then B may not complete the trigger sequence. This occurs when A and B are in the instruction queue at the same time. Basically the A trigger has not yet occurred, so the B instruction is not tagged. Generally, if address B is at
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 493
Chapter 18 Debug Module (DBGV1)
least six addresses higher than address A (or B is lower than A) and there are not changes of flow to put these in the queue at the same time, then this operation should trigger properly. 18.4.2.5.4 Event-Only B (Store Data)
In the event-only B trigger mode, if the match condition for B is met, the B flag in DBGSC is set and a trigger occurs. The event-only B trigger mode is considered a begin-trigger type and the BEGIN bit in DBGC1 is ignored. Event-only B is incompatible with instruction tagging (TRGSEL = 1), and thus the value of TRGSEL is ignored. Please refer to Section 18.4.2.7, "Storage Memory," for more information. This trigger mode is incompatible with the detail capture mode so the detail capture mode will have priority. TRGSEL and BEGIN will not be ignored and this trigger mode will behave as if it were "B only". 18.4.2.5.5 A then Event-Only B (Store Data)
In the A then event-only B trigger mode, the match condition for A must be met before the match condition for B is compared, after the A match has occurred, a trigger occurs each time B matches. When the match condition for A or B is met, the corresponding flag in DBGSC is set. The A then event-only B trigger mode is considered a begin-trigger type and BEGIN in DBGC1 is ignored. TRGSEL in DBGC1 applies only to the match condition for A. Please refer to Section 18.4.2.7, "Storage Memory," for more information. This trigger mode is incompatible with the detail capture mode so the detail capture mode will have priority. TRGSEL and BEGIN will not be ignored and this trigger mode will be the same as A then B. 18.4.2.5.6 A and B (Full Mode)
In the A and B trigger mode, comparator A compares to the address bus and comparator B compares to the data bus. In the A and B trigger mode, if the match condition for A and B happen on the same bus cycle, both the A and B flags in the DBGSC register are set and a trigger occurs. If TRGSEL = 1, only matches from comparator A are used to determine if the trigger condition is met and comparator B matches are ignored. If TRGSEL = 0, full-word data matches on an odd address boundary (misaligned access) do not work unless the access is to a RAM that manages misaligned accesses in a single clock cycle (which is typical of RAM modules used in HCS12 MCUs). 18.4.2.5.7 A and Not B (Full Mode)
In the A and not B trigger mode, comparator A compares to the address bus and comparator B compares to the data bus. In the A and not B trigger mode, if the match condition for A and not B happen on the same bus cycle, both the A and B flags in DBGSC are set and a trigger occurs. If TRGSEL = 1, only matches from comparator A are used to determine if the trigger condition is met and comparator B matches are ignored. As described in Section 18.4.2.5.6, "A and B (Full Mode)," full-word data compares on misaligned accesses will not match expected data (and thus will cause a trigger in this mode) unless the access is to a RAM that manages misaligned accesses in a single clock cycle.
MC9S12NE64 Data Sheet, Rev. 1.1 494 Freescale Semiconductor
Functional Description
18.4.2.5.8
Inside Range (A  address  B)
In the inside range trigger mode, if the match condition for A and B happen on the same bus cycle, both the A and B flags in DBGSC are set and a trigger occurs. If a match condition on only A or only B occurs no flags are set. If TRGSEL = 1, the inside range is accurate only to word boundaries. If TRGSEL = 0, an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is within the range. 18.4.2.5.9 Outside Range (address < A or address > B)
In the outside range trigger mode, if the match condition for A or B is met, the corresponding flag in DBGSC is set and a trigger occurs. If TRGSEL = 1, the outside range is accurate only to word boundaries. If TRGSEL = 0, an aligned word access which straddles the range boundary will cause a trigger only if the aligned address is outside the range. 18.4.2.5.10 Control Bit Priorities The definitions of some of the control bits are incompatible with each other. Table 18-25 and the notes associated with it summarize how these incompatibilities are managed: * Read/write comparisons are not compatible with TRGSEL = 1. Therefore, RWAEN and RWBEN are ignored. * Event-only trigger modes are always considered a begin-type trigger. See Section 18.4.2.8.1, "Storing with Begin-Trigger," and Section 18.4.2.8.2, "Storing with End-Trigger." * Detail capture mode has priority over the event-only trigger/capture modes. Therefore, event-only modes have no meaning in detail mode and their functions default to similar trigger modes.
Table 18-25. Resolution of Mode Conflicts
Normal / Loop1 Mode Tag A only A or B A then B Event-only B A then event-only B A and B (full mode) A and not B (full mode) Inside range Outside range 1 2 5 5 6 6 1, 3 4 5 5 6 6 3 4 Force Tag Force Detail
1 -- Ignored -- same as force 2 -- Ignored for comparator B 3 -- Reduces to effectively "B only" 4 -- Works same as A then B 5 -- Reduces to effectively "A only" -- B not compared 6 -- Only accurate to word boundaries
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 495
Chapter 18 Debug Module (DBGV1)
18.4.2.6
Capture Modes
The DBG in DBG mode can operate in four capture modes. These modes are described in the following subsections. 18.4.2.6.1 Normal Mode
In normal mode, the DBG module uses comparator A and B as triggering devices. Change-of-flow information or data will be stored depending on TRG in DBGSC. 18.4.2.6.2 Loop1 Mode
The intent of loop1 mode is to prevent the trace buffer from being filled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after address information is placed in the trace buffer, the DBG module writes this value into the C comparator and the C comparator is placed in ignore address mode. This will prevent duplicate address entries in the trace buffer resulting from repeated bit-conditional branches. Comparator C will be cleared when the ARM bit is set in loop1 mode to prevent the previous contents of the register from interfering with loop1 mode operation. Breakpoints based on comparator C are disabled. Loop1 mode only inhibits duplicate source address entries that would typically be stored in most tight looping constructs. It will not inhibit repeated entries of destination addresses or vector addresses, because repeated entries of these would most likely indicate a bug in the user's code that the DBG module is designed to help find. NOTE In certain very tight loops, the source address will have already been fetched again before the C comparator is updated. This results in the source address being stored twice before further duplicate entries are suppressed. This condition occurs with branch-on-bit instructions when the branch is fetched by the first P-cycle of the branch or with loop-construct instructions in which the branch is fetched with the first or second P cycle. See examples below:
LOOP INCX ; 1-byte instruction fetched by 1st P-cycle of BRCLR BRCLR CMPTMP,#$0c,LOOP ; the BRCLR instruction also will be fetched by 1st P-cycle of BRCLR * A,LOOP2 ; 2-byte instruction fetched by 1st P-cycle of DBNE ; 1-byte instruction fetched by 2nd P-cycle of DBNE ; this instruction also fetched by 2nd P-cycle of DBNE
LOOP2 BRN NOP DBNE
NOTE Loop1 mode does not support paged memory, and inhibits duplicate entries in the trace buffer based solely on the CPU address. There is a remote possibility of an erroneous address match if program flow alternates between paged and unpaged memory space.
MC9S12NE64 Data Sheet, Rev. 1.1 496 Freescale Semiconductor
Functional Description
18.4.2.6.3
Detail Mode
In the detail mode, address and data for all cycles except program fetch (P) and free (f) cycles are stored in trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where his code was in error. 18.4.2.6.4 Profile Mode
This mode is intended to allow a host computer to poll a running target and provide a histogram of program execution. Each read of the trace buffer address will return the address of the last instruction executed. The DBGCNT register is not incremented and the trace buffer does not get filled. The ARM bit is not used and all breakpoints and all other debug functions will be disabled.
18.4.2.7
Storage Memory
The storage memory is a 64 words deep by 16-bits wide dual port RAM array. The CPU accesses the RAM array through a single memory location window (DBGTBH:DBGTBL). The DBG module stores trace information in the RAM array in a circular buffer format. As data is read via the CPU, a pointer into the RAM will increment so that the next CPU read will receive fresh information. In all trigger modes except for event-only and detail capture mode, the data stored in the trace buffer will be change-of-flow addresses. change-of-flow addresses are defined as follows: * Source address of conditional branches (long, short, BRSET, and loop constructs) taken * Destination address of indexed JMP, JSR, and CALL instruction * Destination address of RTI, RTS, and RTC instructions * Vector address of interrupts except for SWI and BDM vectors In the event-only trigger modes only the 16-bit data bus value corresponding to the event is stored. In the detail capture mode, address and then data are stored for all cycles except program fetch (P) and free (f) cycles.
18.4.2.8
18.4.2.8.1
Storing Data in Memory Storage Buffer
Storing with Begin-Trigger
Storing with begin-trigger can be used in all trigger modes. When DBG mode is enabled and armed in the begin-trigger mode, data is not stored in the trace buffer until the trigger condition is met. As soon as the trigger condition is met, the DBG module will remain armed until 64 words are stored in the trace buffer. If the trigger is at the address of the change-of-flow instruction the change-of-flow associated with the trigger event will be stored in the trace buffer. 18.4.2.8.2 Storing with End-Trigger
Storing with end-trigger cannot be used in event-only trigger modes. When DBG mode is enabled and armed in the end-trigger mode, data is stored in the trace buffer until the trigger condition is met. When the trigger condition is met, the DBG module will become de-armed and no more data will be stored. If
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 497
Chapter 18 Debug Module (DBGV1)
the trigger is at the address of a change-of-flow address the trigger event will not be stored in the trace buffer.
18.4.2.9
Reading Data from Trace Buffer
The data stored in the trace buffer can be read using either the background debug module (BDM) module or the CPU provided the DBG module is enabled and not armed. The trace buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of valid words can be determined. CNT will not decrement as data is read from DBGTBH:DBGTBL. The trace buffer data is read by reading DBGTBH:DBGTBL with a 16-bit read. Each time DBGTBH:DBGTBL is read, a pointer in the DBG will be incremented to allow reading of the next word. Reading the trace buffer while the DBG module is armed will return invalid data and no shifting of the RAM pointer will occur. NOTE The trace buffer should be read with the DBG module enabled and in the same capture mode that the data was recorded. The contents of the trace buffer counter register (DBGCNT) are resolved differently in detail mode verses the other modes and may lead to incorrect interpretation of the trace buffer data.
18.4.3
Breakpoints
There are two ways of getting a breakpoint in DBG mode. One is based on the trigger condition of the trigger mode using comparator A and/or B, and the other is using comparator C. External breakpoints generated using the TAGHI and TAGLO external pins are disabled in DBG mode.
18.4.3.1
Breakpoint Based on Comparator A and B
A breakpoint request to the CPU can be enabled by setting DBGBRK in DBGC1. The value of BEGIN in DBGC1 determines when the breakpoint request to the CPU will occur. When BEGIN in DBGC1 is set, begin-trigger is selected and the breakpoint request will not occur until the trace buffer is filled with 64 words. When BEGIN in DBGC1 is cleared, end-trigger is selected and the breakpoint request will occur immediately at the trigger cycle. There are two types of breakpoint requests supported by the DBG module, tagged and forced. Tagged breakpoints are associated with opcode addresses and allow breaking just before a specific instruction executes. Forced breakpoints are not associated with opcode addresses and allow breaking at the next instruction boundary. The type of breakpoint based on comparators A and B is determined by TRGSEL in the DBGC1 register (TRGSEL = 1 for tagged breakpoint, TRGSEL = 0 for forced breakpoint). Table 18-26 illustrates the type of breakpoint that will occur based on the debug run.
MC9S12NE64 Data Sheet, Rev. 1.1 498 Freescale Semiconductor
Resets
Table 18-26. Breakpoint Setup
BEGIN 0 0 0 0 1 1 1 1 TRGSEL 0 0 1 1 0 0 1 1 DBGBRK 0 1 0 1 0 1 0 1 Type of Debug Run Fill trace buffer until trigger address (no CPU breakpoint -- keep running) Fill trace buffer until trigger address, then a forced breakpoint request occurs Fill trace buffer until trigger opcode is about to execute (no CPU breakpoint -- keep running) Fill trace buffer until trigger opcode about to execute, then a tagged breakpoint request occurs Start trace buffer at trigger address (no CPU breakpoint -- keep running) Start trace buffer at trigger address, a forced breakpoint request occurs when trace buffer is full Start trace buffer at trigger opcode (no CPU breakpoint -- keep running) Start trace buffer at trigger opcode, a forced breakpoint request occurs when trace buffer is full
18.4.3.2
Breakpoint Based on Comparator C
A breakpoint request to the CPU can be created if BKCEN in DBGC2 is set. Breakpoints based on a successful comparator C match can be accomplished regardless of the mode of operation for comparator A or B, and do not affect the status of the ARM bit. TAGC in DBGC2 is used to select either tagged or forced breakpoint requests for comparator C. Breakpoints based on comparator C are disabled in LOOP1 mode. NOTE Because breakpoints cannot be disabled when the DBG is armed, one must be careful to avoid an "infinite breakpoint loop" when using tagged-type C breakpoints while the DBG is armed. If BDM breakpoints are selected, executing a TRACE1 instruction before the GO instruction is the recommended way to avoid re-triggering a breakpoint if one does not wish to de-arm the DBG. If SWI breakpoints are selected, disarming the DBG in the SWI interrupt service routine is the recommended way to avoid re-triggering a breakpoint.
18.5
Resets
The DBG module is disabled after reset. The DBG module cannot cause a MCU reset.
18.6
Interrupts
The DBG contains one interrupt source. If a breakpoint is requested and BDM in DBGC2 is cleared, an SWI interrupt will be generated.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 499
Chapter 18 Debug Module (DBGV1)
MC9S12NE64 Data Sheet, Rev. 1.1 500 Freescale Semiconductor
Appendix A Electrical Characteristics
NOTE The MC9S12NE64 is specified and tested at the 3.3-V range. This section contains the most accurate electrical information for the MC9S12NE64 microcontroller available at the time of publication. The information is subject to change. This introduction is intended to give an overview on several common topics like power supply, current injection etc.
A.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate, under the "C" column heading. P: Those parameters are guaranteed during production testing on each individual device. C: Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. They are regularly verified by production monitors. T: Those parameters are achieved by design characterization on a small sample size from typical devices. All values shown in the typical column are within this category. D: Those parameters are derived mainly from simulations.
A.2
Power Supply
The MC9S12NE64 uses several pins to supply power to the I/O ports, A/D converter, oscillator and PLL, the Ethernet Physical Transceiver (EPHY), as well as the digital core. * * * * * * * * * The VDDA, VSSA pair supplies the A/D converter and portions of the EPHY The VDDX1, VDDX2, VSSX1, VSSX2 pairs supply the I/O pins, and internal voltage regulator The VDDR supplies the internal voltage regulator, and is the VREGEN signal VDD1, VSS1, VDD2, and VSS2 are the supply pins for the digital logic VDDPLL, VSSPLL supply the oscillator and the PLL VSS1 and VSS2 are internally connected by metal VDD1 and VDD2 are internally connected by metal PHY_VDDA, PHY_VSSA are power supply pins for EPHY analog PHY_VDDRX, PHY_VSSRX are power supply pins for EPHY receiver
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 501
Appendix A Electrical Characteristics
* *
PHY_VDDTX, PHY_VSSTX are power supply pins for EPHY transmitter VDDA, VDDX1, VDDX2 as well as VSSA, VSSX1, VSSX2 are connected by anti-parallel diodes for ESD protection. NOTE In the following context: * * * * * * * * * * VDD3 is used for either VDDA, VDDR, and VDDX1/VDDX2 VSS3 is used for either VSSA, VSSR, and VSSX1/VSSX2 unless otherwise noted IDD3 denotes the sum of the currents flowing into the VDDA, VDDR, and VDDX1/VDDX2 pins VDD is used for VDD1, VDD2, VDDPLL, PHY_VDDTX, PHY_VDDRX, and PHY_VDDA VSS is used for VSS1, VSS2, VSSPL, PHY_VSSTX, PHY_VSSRX, and PHY_VSSA IDD is used for the sum of the currents flowing into VDD1, VDD2 IDDPHY is used for the sum of currents flowing into PHY_VDDTX, PHY_VDDRX, and PHY_VDDA VDDPHY is used for PHY_VDDTX, PHY_VDDRX, and PHY_VDDA VDDTX is used for twisted pair differential voltage present on the PHY_TXP and PHY_TXN pins IDDTX is used for twisted pair differential current flowing into the PHY_TXP or PHY_TXN pins
A.3
A.3.1
Pins
3.3 V I/O Pins
There are four groups of functional pins.
These I/O pins have a nominal level of 3.3 V. This group of pins is comprised of all port I/O pins, the analog inputs, BKGD pin and the RESET inputs. The internal structure of these pins are identical, however some of the functionality may be disabled.
A.3.2
Analog Reference, Special Function Analog
This group of pins is comprised of the VRH, VRL, PHY_TXN, PHY_TXP, PHY_RXN, PHY_RXP, and RBIAS pins.
MC9S12NE64 Data Sheet, Rev. 1.1 502 Freescale Semiconductor
Current Injection
A.3.3
Oscillator
The pins XFC, EXTAL, XTAL dedicated to the oscillator have a nominal 2.5 V level. They are supplied by VDDPLL.
A.3.4
TEST
This pin is used for production testing only, and should be tied to ground during normal operation.
A.4
Current Injection
Power supply must maintain regulation within operating VDD3 or VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD3) is greater than IDD3, the injection current may flow out of VDD3 and could result in external power supply going out of regulation. Ensure external VDD3 load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if clock rate is very low, which would reduce overall power consumption.
A.5
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS3 or VDD3).
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 503
Appendix A Electrical Characteristics
Table A-1. Absolute Maximum Ratings
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5
Rating
I/O, Regulator and Analog Supply Voltage Digital Logic Supply Voltage 1 PLL Supply Voltage 1 Voltage difference VDDX to VDDR and VDDA Voltage difference VSSX to VSSR and VSSA Digital I/O Input Voltage Analog Reference XFC, EXTAL, XTAL inputs TEST input Instantaneous Maximum Current Single pin limit for all digital I/O pins 2 Instantaneous Maximum Current Single pin limit for XFC, EXTAL, XTAL 3 Instantaneous Maximum Current Single pin limit for TEST 4 Operating Temperature Range (ambient) Operating Temperature Range (junction) Storage Temperature Range
Symbol
VDD3 VDD VDDPLL VDDX VSSX VIN VRH, VRL VILV VTEST I I
D
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -25 -25 -0.25 -40 -40 -65
Max
4.5 3.0 3.0 0.3 0.3 6.5 6.5 3.0 10.0 +25 +25 0 105 5 140 155
Unit
V V V V V V V V V mA mA mA C C C
DL
IDT TA TJ T
stg
The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source. All digital I/O pins are internally clamped to VSSX and VDDX, VDDR or VSSA and VDDA. These pins are internally clamped to VSSPLL and VDDPLL. This pin is clamped low to VSSPLL, but not clamped high. This pin must be tied low in applications. Maximum ambient temperature is package dependent.
A.6
ESD Protection and Latch-Up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 stress test qualification for automotive grade integrated circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM), and the charge device model. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
MC9S12NE64 Data Sheet, Rev. 1.1 504 Freescale Semiconductor
ESD Protection and Latch-Up Immunity
Table A-2. ESD and Latch-Up Test Conditions
Model
Series Resistance Storage Capacitance Human Body Number of Pulse per pin positive negative Series Resistance Storage Capacitance Machine Number of Pulse per pin positive negative Minimum input voltage limit Latch-up Maximum input voltage limit 7.5 V
Description
Symbol
R1 C -- R1 C --
Value
1500 100 -- 3 3 0 200 -- 3 3 -2.5
Unit
 pF
 pF
V
Table A-3. ESD and Latch-Up Protection Characteristics
Num
1
C
C
Rating
Human Body Model (HBM) Only PHY_TXP, PHY_TXN, PHY_RXP, PHY_RXN pins Machine Model (MM)
Symbol
VHBM
Min
2000 1000 200
Max
-- -- -- -- -- --
Unit
V V V V V V
2
C
Only PHY_TXP, PHY_TXN, PHY_RXP, PHY_RXN pins Charge Device Model (CDM)
VMM
100 500
3
C
Only PHY_TXP, PHY_TXN, PHY_RXP, PHY_RXN pins Latch-up Current at 125C positive negative Latch-up Current at 27C positive negative
VCDM
250
4
C
ILAT
+100 -100 +200 -200
--
mA
5
C
ILAT
--
mA
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 505
Appendix A Electrical Characteristics
A.7
Operating Conditions
This section describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE Instead of specifying ambient temperature, all parameters are specified for the more meaningful silicon junction temperature. For power dissipation calculations refer to Section A.8, "Power Dissipation and Thermal Characteristics."
Table A-4. Operating Conditions
Rating
I/O and Regulator Supply Voltage Analog Supply Voltage Regulator Supply Voltage Digital Logic Supply Voltage 1 PLL Supply Voltage 1 Voltage Difference VDDX1/VSSX2 to VDDA Voltage Difference VSSX/VSSX2 to VSSA Oscillator 2 Bus Frequency Operating Junction Temperature Range
1
Symbol
VDDX VDDA VDDR VDD VDDPLL VDDX VSSX fosc fbus T
J
Min
3.135 3.135 3.135 2.375 2.375 -0.1 -0.1 0.5 0.5 -40
Typ
3.3 3.3 3.3 2.5 2.5 0 0 -- -- --
Max
3.465 3.465 3.465 2.625 2.625 0.1 0.1 25 25 125
Unit
V V V V V V V MHz MHz C
The device contains an internal voltage regulator to generate VDD1, VDD2, VDDPLL, PHY_VDDRX, PHY_VDDTX and PHY_VDDA supplies out of the VDDX and VDDR supply. The absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. 2 For the internal Ethernet physical transceiver (EPHY) to operate properly a 25 MHz oscillator is required.
A.8
Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum operating junction temperature is not exceeded. The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D *  JA ) T J = Junction Temperature, [C ] T A = Ambient Temperature, [C ] P D = Total Chip Power Dissipation, [W]
MC9S12NE64 Data Sheet, Rev. 1.1 506 Freescale Semiconductor
Power Dissipation and Thermal Characteristics
 JA = Package Thermal Resistance, [C/W]
The total power dissipation can be calculated from:
P D = P INT + P IO P INT = Chip Internal Power Dissipation, [W]
Two cases with internal voltage regulator enabled and disabled must be considered: 1. Internal Voltage Regulator disabled
P INT =I DD V DD +I DDPLL V DDPLL +I DDA V DDA +I DDPHY V DDPHY +I DDTX V DDTX
P IO =
i
R DSON  I IO
2 i
Which is the sum of all output currents on I/O ports associated with VDDX. For RDSON is valid:
V OL R DSON = ----------- ;for outputs driven low I OL
respectively
V DD3 ( 5 ) - V OH R DSON = ------------------------------------------- ;for outputs driven high I OH
2. Internal voltage regulator enabled
P INT =I DDR V DDR +I DDA V DDA +I DDX V DDX +I DDTX V DDTX
IDDX is the current shown in Table A-7 and not the overall current flowing into VDDX, which additionally contains the current flowing into the external loads with output high.
P IO =
 RDSON  IIOi
i
2
Which is the sum of all output currents on I/O ports associated with VDDX.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 507
Appendix A Electrical Characteristics
Table A-5. Thermal Package Characteristics 1
Num
1 2 3 4 5 6 7 8 9 10 6 7 8 9 10
1 2
C
T T T T T T T T T T T T T T T
Rating
Thermal Resistance LQFP112, single sided PCB 2 Thermal Resistance LQFP112, double sided PCB with two internal planes 3 Junction to Board LQFP112 Junction to Case LQFP112 Junction to Package Top LQFP112 Thermal Resistance TQFP-EP80, single sided PCB Thermal Resistance TQFP-EP80, double sided PCB with two internal planes Junction to Board TQFP-EP80 Junction to Case TQFP-EP80 Junction to Package Top TQFP-EP80 Thermal Resistance Epad TQFP-EP80, single sided PCB Thermal Resistance Epad TQFP-EP80, double sided PCB with two internal planes Junction to Board TQFP-EP80 Junction to Case TQFP-EP80 4 Junction to Package Top TQFP-EP80
Symbol
JA JA JB JC JT JA JA JB JC JT JA JA JB JC JT
Min
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ
-- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max
54 41 31 11 2 51 41 27 14 3 48 24 10 0.7 2
Unit
oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W
The values for thermal resistance are achieved by package simulations PC Board according to EIA/JEDEC Standard 51-3 3 PC Board according to EIA/JEDEC Standard 51-7 4 Thermal resistance between the die and the exposed die pad.
A.9
I/O Characteristics
This section describes the characteristics of all 3.3 V I/O pins. All parameters are not always applicable; e.g., not all pins feature pullup/pulldown resistances.
MC9S12NE64 Data Sheet, Rev. 1.1 508 Freescale Semiconductor
I/O Characteristics
Table A-6. Preliminary 3.3 V I/O Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1
C
P T P Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input Hysteresis
Rating
Symbol
V
IH
Min
0.65*VDD3 -- -- VSS3 - 0.3
Typ
-- -- -- -- 250
Max
-- VDD3 + 0.3 0.35*VDD3 --
Unit
V V V V mV A
VIH V
IL
2 T 3 C V
VIL
HYS
4
P
Input Leakage Current (pins in high ohmic input mode) 1 Vin = VDD5 or VSS5 Output High Voltage (pins in output mode) Partial Drive IOH = -0.75 mA Output High Voltage (pins in output mode) Full Drive IOH = -4.5 mA Output Low Voltage (pins in output mode) Partial Drive IOL = +0.9 mA Output Low Voltage (pins in output mode) Full Drive IOL = +5.5 mA Internal Pull Up Device Current, tested at V Max.
IL
Iin
-2.5
--
2.5
5
C
V
OH
VDD3 - 0.4 VDD3 - 0.4
--
--
V
6
P
V
OH
--
--
V
7
C
V
OL
--
--
0.4
V
8
P
VOL IPUL IPUH IPDH IPDL Cin IICS IICP tPIGN tPVAL
--
--
0.4
V A A A A pF  s s
9
P
--
--
-60
10
C
Internal Pull Up Device Current, tested at V Min.
IH
-6
--
--
11
P
Internal Pull Down Device Current, tested at V Min.
IH
--
--
60
12 13 14 15 16
1
C D T P P
Internal Pull Down Device Current, tested at V Max.
IL
6
-- 7
-- -- 2.5 25 3
Input Capacitance Injection current 2 Single Pin limit Total Device Limit. Sum of all injected currents Port G, H, and J Interrupt Input Pulse filtered 3 Port G, H, and J Interrupt Input Pulse passed3
-2.5 -25
--
10
Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half for each 8C to 12C in the temperature range from 50C to 125C. 2 Refer to Section A.4, "Current Injection," for more details. 3 Parameter only applies in stop or pseudo stop mode.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 509
Appendix A Electrical Characteristics
A.10 Supply Currents
This section describes the current consumption characteristics of the device as well as the conditions for the measurements.
A.10.1 Measurement Conditions
All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25 MHz bus frequency using a 25 MHz oscillator.
A.10.2 Additional Remarks
In expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. No generally applicable numbers can be given. A very good estimate is to take the single chip currents and add the currents due to the external loads.
Table A-7. Supply Current Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
C
P C P C C C P C P C C
Rating
Run supply currents Single chip, internal regulator enabled, EPHY disabled Single chip, internal regulator enabled, EPHY auto negotiate 1 Single chip, internal regulator enabled, EPHY 100BASE-TX1 Single chip, internal regulator enabled, EPHY 10BASE-T1 Wait supply current All modules enabled All modules but EPHY enabled only RTI enabled Pseudo stop current (RTI and COP enabled) -40C 27C 85C 105C Pseudo stop current (RTI and COP disabled) -40C 27C 85C 105C Stop current -40C 27C 85C 105C
Symbol
Min
Typ
Max
65 285 265 185 270 50 5
Unit
1
IDD3
mA
2
IDDW
mA
3
IDDPS
600 600 1000 1000 160 160 700 700 60 60 400 500
750 5000
A
4
C C C C C P C C
IDDPS
400 5000
A
5
IDDS
200 5000
A
1
When calculating power consumption, the additional current sunk by the PHY_TXN and PHY_TXP pins must be taken into account. See Table A-8 for currents and voltages to use in the power calculations.
MC9S12NE64 Data Sheet, Rev. 1.1 510 Freescale Semiconductor
Supply Currents
Table A-8. EPHY Twisted Pair Transmit Pin Characteristics
Num
1
C
C
Rating
Auto-negotiate transmitter current
Symbol
IDDTX
Min
Typ
130
Max
Unit
mA
2
C
Auto-negotiate transmitter voltage
VDDTX
VDD3 - 1.1 V
V
3
C
10BASE-T mode transmitter current
IDDTX
130
mA
4
C
10BASE-T mode transmitter voltage
VDDTX 45
VDD3 - 1.1 V
V
5
C
100BASE-TX mode transmitter current
IDDTX
mA
6
C
100BASE-TX mode transmitter voltage
VDDTX
VDD3 - 0.95 V
V
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 511
Appendix A Electrical Characteristics
A.11
ATD Electrical Characteristics
This section describes the characteristics of the analog-to-digital converter.
A.11.1
ATD Operating Characteristics -- 3.3 V Range
Table 18-27 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: VSSA  VRL  VIN  VRH  VDDA. This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. If the input level goes outside of this range it will effectively be clipped.
Table 18-27. 3.3V ATD Operating Characteristics
Conditions are shown in Table A-4 unless otherwise noted; Supply Voltage 3.3 V-10% <= VDDA <= 3.3 V +10%
Num C
1 D Reference Potential
Rating
Low High
Symbol
VRL VRH VRH-VRL fATDCLK NCONV10 TCONV10 NCONV8 TCONV8 tREC IREF
Min
VSSA VDDA/2 3.0 0.5 14 7
Typ
Max
VDDA/2 VDDA
Unit
V V V MHz Cycles s Cycles s s mA
2 3 4
C Differential Reference Voltage D ATD Clock Frequency D ATD 10-Bit Conversion Period Clock Cycles 1 Conv, Time at 2.0 MHz ATD Clock fATDCLK
3.3
3.6 2.0 28 14
5
D ATD 8-Bit Conversion Period Clock Cycles1 Conv, Time at 2.0 MHz ATD Clock fATDCLK 12 6 26 13 20 0.250
6 7
1
D Recovery Time (VDDA = 3.3 V) P Reference Supply current
The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks.
A.11.2
Factors Influencing Accuracy
Three factors -- source resistance, source capacitance, and current injection -- have an influence on the accuracy of the ATD.
A.11.2.1
Source Resistance
Due to the input pin leakage current as specified in Table A-6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input. The maximum source resistance RS specifies results in an error of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance are allowed.
MC9S12NE64 Data Sheet, Rev. 1.1 512 Freescale Semiconductor
ATD Electrical Characteristics
A.11.2.2
Source Capacitance
When sampling an additional internal capacitor is switched to the input. This can cause a voltage drop due to charge sharing with the external and the pin capacitance. For a maximum sampling error of the input voltage  1LSB, then the external filter capacitor, Cf  1024 * (CINS- CINN).
A.11.2.3
Current Injection
There are two cases to consider. * A current is injected into the channel being converted. The channel being stressed has conversion values of $3FF ($FF in 8-bit mode) for analog inputs greater than VRH and $000 for values less than VRL unless the current is higher than specified as disruptive conditions. * Current is injected into pins in the neighborhood of the channel being converted. A portion of this current is picked up by the channel (coupling ratio K), This additional current impacts the accuracy of the conversion depending on the source resistance. The additional input voltage error on the converted channel can be calculated as VERR = K * RS * IINJ, with IINJ being the sum of the currents injected into the two pins adjacent to the converted channel.
Table A-9. ATD Electrical Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2
C
C T
Rating
Max input Source Resistance Total Input Capacitance Non Sampling Sampling Disruptive Analog Input Current Coupling Ratio positive current injection Coupling Ratio negative current injection
Symbol
RS CINN CINS INA Kp Kn
Min
--
Typ
--
Max
1 10 15
Unit
k pF
3 4 5
C C C
-2.5
2.5 10-4 10-2
mA A/A A/A
A.11.3
ATD Accuracy -- 3.3 V Range
Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 513
Appendix A Electrical Characteristics
Table A-10. 3.3-V A/D Conversion Performance
Conditions are shown in Table A-4 unless otherwise noted VREF = VRH - VRL = 3.328 V. Resulting to one 8 bit count = 13 mV and one 10 bit count = 3.25 mV fATDCLK = 2.0 MHz
Num C
1 2 3 4 5 6 7 8 9
1
Rating
Symbol
LSB DNL INL AE AE LSB DNL INL AE
Min
Typ
3.25
Max
Unit
mV
P 10-Bit Resolution P 10-Bit Differential Nonlinearity P 10-Bit Integral Nonlinearity P 10-Bit Absolute Error 1 C 10-Bit Absolute Error at fATDCLK= 4MHz P 8-Bit Resolution P 8-Bit Differential Nonlinearity P 8-Bit Integral Nonlinearity P 8-Bit Absolute Error1
-1.5 -3.5 -5 1.5 2.5 7.0 13 -0.5 -1.5 -2.0 1.0 1.5
1.5 3.5 5
Counts Counts Counts Counts mV
0.5 1.5 2.0
Counts Counts Counts
These values include the quantization error which is inherently 1/2 count for any A/D converter.
For the following definitions see also Figure A-1. Differential non-linearity (DNL) is defined as the difference between two adjacent switching steps.
Vi - Vi - 1 DNL ( i ) = ------------------------ - 1 1LSB
The integral non-linearity (INL) is defined as the sum of all DNLs: n
INL ( n ) =
i=1
Vn - V0 DNL ( i ) = ------------------- - n 1LSB
MC9S12NE64 Data Sheet, Rev. 1.1 514 Freescale Semiconductor
ATD Electrical Characteristics
DNL
LSB Vi-1
$3FF $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5
10-Bit Absolute Error Boundary Vi 8-Bit Absolute Error Boundary
$FF
$FE
10-Bit Resolution
$3F4 $3F3
$FD
9 8 7 6 5 4 3 2 1 0 5 10 15 20 25 30 35 40 50
Ideal Transfer Curve
2
10-Bit Transfer Curve
1
8-Bit Transfer Curve
5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120
Vin mV
Figure A-1. ATD Accuracy Definitions
NOTE Figure A-1 shows only definitions, for specification values refer to Table A-10.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 515
8-Bit Resolution
Appendix A Electrical Characteristics
A.12
Reset, Oscillator, and PLL Electrical Characteristics
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked loop (PLL).
A.12.1
Startup
Table A-11 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the clock and reset generator (CRG) block description chapter.
Table A-11. Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5 6 7 8
C
T T D D D D P P POR release level POR assert level
Rating
Symbol
VPORR VPORA PWRSTL nRST PWIRQ tWRS VLVRR VLVRA
Min
Typ
Max
2.07
Unit
V V tosc
0.97 2 192 20 14 2.25 2.55 196
Reset input pulse width, minimum input time Startup from Reset Interrupt pulse width, IRQ edge-sensitive mode Wait recovery startup time LVR release level LVR assert level
nosc ns tcyc V V
A.12.1.1
POR
The release level VPORR and the assert level VPORA are derived from the VDD supply. They are also valid if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc.
A.12.1.2
LVR
The release level VLVRR and the assert level VLVRA are derived from the VDD supply. They are also valid if the device is powered externally. After releasing the LVR reset the oscillator and the clock quality check are started. If after a time tCQOUT no valid oscillation is detected, the MCU will start using the internal self clock. The fastest startup time possible is given by nuposc.
A.12.1.3
SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG flags register has not been set.
MC9S12NE64 Data Sheet, Rev. 1.1 516 Freescale Semiconductor
Reset, Oscillator, and PLL Electrical Characteristics
A.12.1.4
External Reset
When external reset is asserted for a time greater than PWRSTL the CRG module generates an internal reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset.
A.12.1.5
Stop Recovery
Out of stop, the controller can be woken up by an external interrupt. A clock quality check as after POR is performed before releasing the clocks to the system.
A.12.1.6
Pseudo Stop and Wait Recovery
The recovery from pseudo stop and wait are essentially the same because the oscillator was not stopped in either mode. The controller can be woken up by internal or external interrupts. After twrs the CPU starts fetching the interrupt vector.
A.12.2
Oscillator
The device features an internal Pierce oscillator. Before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP or oscillator fail. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a clock monitor. A clock monitor failure is asserted if the frequency of the incoming clock signal is below the assert frequency fCMFA.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 517
Appendix A Electrical Characteristics
Table A-12. Oscillator Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
1 2 3 4 5 6 7 8 9 10 11 12
Rating
Symbol
fOSC iOSC tUPOSC tCQOUT fCMFA fEXT tEXTL tEXTH tEXTR tEXTF CIN VDCBIAS V IH,EXTAL V IH,EXTAL V IL,EXTAL V IL,EXTAL VHYS,EXTAL
Min
0.5 100
Typ
Max
40
Unit
MHz A
C Crystal oscillator range (Pierce) 1, 2 P Startup current C Oscillator start-up time (Pierce) D Clock quality check time-out P Clock monitor failure assert frequency P External square wave input frequency 2 D External square wave pulse width low D External square wave pulse width high D External square wave rise time D External square wave fall time D Input capacitance (EXTAL, XTAL pins) C DC operating bias in Colpitts configuration on EXTAL pin EXTAL pin input high voltage4 EXTAL pin input high voltage4 EXTAL pin input low voltage4 EXTAL pin input low voltage4 EXTAL pin input hysteresis4
83 0.45 50 0.5 9.5 9.5 100
100 4 2.5 200 50
ms s kHz MHz ns ns
1 1 7 1.1 0.7*VDDPLL VDDPLL+ 0.3 0.3*VDDPLL VSSPLL- 0.3 250
ns ns pF V V V V V mV
Depending on the crystal a damping series resistor might be necessary XCLKS =0 during reset 3f osc = 25 MHz, C = 22 pF. 4 Maximum value is for extreme cases using high Q, low frequency crystals
2
1
A.12.3
Phase-Locked Loop
The oscillator provides the reference clock for the PLL. The PLLs voltage controlled oscillator (VCO) is also the system clock source in self clock mode.
A.12.3.1
XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
MC9S12NE64 Data Sheet, Rev. 1.1 518 Freescale Semiconductor
Reset, Oscillator, and PLL Electrical Characteristics
Cp VDDPLL Cs fosc fref 1 refdv+1  fcmp R Phase K Detector Loop Divider 1 synr+1
Figure 18-22. Basic PLL Functional Diagram
XFC Pin
VCO KV fvco
1 2
The following procedure can be used to calculate the resistance and capacitance values using typical values for K1, f1 and ich from Table A-13. The grey boxes show the calculation for fVCO = 50 MHz and fref = 1 MHz. E.g., these frequencies are used for fOSC = 4 MHz and a 25 MHz bus clock. The VCO Gain at the desired VCO frequency is approximated by: ( f 1 - f vco ) ---------------------K 1  1V ( 60 - 50 ) ---------------------- 100
KV = K1  e
= - 100  e
= -90.48MHz/V
The phase detector relationship is given by:
K  = - i ch  K V
ich is the current in tracking mode.
= 316.7Hz/
The loop bandwidth fC should be chosen to fulfill the Gardner's stability criteria by at least a factor of 10, typical values are 50.  = 0.9 ensures a good transient response.
2    f ref f ref 1 f C < ------------------------------------------ -----  f C < ------------ ;(  = 0.9 ) 4  10 10 2    + 1 +   fC < 25kHz  
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 519
Appendix A Electrical Characteristics
And finally the frequency relationship is defined as:
f VCO n = ------------ = 2  ( synr + 1 ) f ref
= 50
With the above values the resistance can be calculated. The example is shown for a loop bandwidth fC = 10 kHz:
2    n  fC R = ---------------------------- = 2**50*10kHz/(316.7Hz/)=9.9k=~10k K
The capacitance Cs can now be calculated as:
0.516 2 C s = ---------------------  -------------- ;(  = 0.9 ) = 5.19nF =~ 4.7nF   fC  R fC  R
The capacitance Cp should be chosen in the range of:
2
C s  20  C p  C s  10
Cp = 470pF
A.12.3.1.1 Jitter Information The basic functionality of the PLL is shown in Figure 18-22. With each transition of the clock fcmp, the deviation from the reference clock fref is measured and input voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes in the clock output frequency. Noise, voltage, temperature, and other factors cause slight variations in the control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure 18-23. 0 1 2 3 N-1 N
tmin1 tnom tmax1 tminN tmaxN
Figure 18-23. Jitter Definitions
MC9S12NE64 Data Sheet, Rev. 1.1 520 Freescale Semiconductor
Reset, Oscillator, and PLL Electrical Characteristics
The relative deviation of tnom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as:
t max ( N ) t min ( N )   J ( N ) = max  1 - -------------------- , 1 - --------------------  N  t nom N  t nom  
For N < 100, the following equation is a good fit for the maximum jitter:
j1 J ( N ) = ------- + j 2 N
J(N)
1
5
10
20
N
This is very important to notice with respect to timers, serial modules where a prescaler will eliminate the effect of the jitter to a large extent.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 521
Appendix A Electrical Characteristics
Table A-13. PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2
C
P D D D D D C D D D D D D C C
Rating
Self clock mode frequency VCO locking range Lock detector transition from acquisition to tracking mode Lock detection Unlock detection Lock detector transition from tracking to acquisition mode PLLON total stabilization delay (auto mode) 2 PLLON acquisition mode stabilization delay 2 PLLON tracking mode stabilization delay 2 Fitting parameter VCO loop gain Fitting parameter VCO loop frequency Charge pump current acquisition mode Charge pump current tracking mode Jitter fit parameter 12 Jitter fit parameter 22
Symbol
fSCM fVCO |trk| |Lock| |unl| |unt| tstab tacq tal K1 f1 | ich | | ich | j1 j2
Min
1 8 3 0 0.5 6
Typ
Max
5.5 50 4 1.5 2.5 8
Unit
MHz MHz %1 %1 %1 %1 ms ms ms MHz/V MHz A A
0.5 0.3 0.2 -100 60 38.5 3.5 1.1 0.13
% %
% deviation from target frequency fREF = 25 MHz, fBUS = 25 MHz equivalent fVCO = 50 MHz: REFDV = #$00, SYNR = #$00, Cs = 4700 pF, Cp = 470 pF, Rs = 2.2 k.
MC9S12NE64 Data Sheet, Rev. 1.1 522 Freescale Semiconductor
EMAC Electrical Characteristics
A.13
EMAC Electrical Characteristics
NOTE The electrical characteristics given in the EMAC section are preliminary and should be used as a guide only. Values cannot be guaranteed by Freescale Semiconductor and are subject to change without notice.
A.13.1
MII Timing
The following MII timing is based on IEEE Std 802.3.
A.13.1.1
MII Receive Signal Timing (MII_RXD[3:0], MII_RXDV, MII_RXER, MII_RXCLK)
Table A-14. MII Receive Signal Timing
Num M1 M2 M3 M4
Characteristic RXD[3:0], RXDV, RXER setup to RXCLK rise RXCLK rise to RXD[3:0], RXDV, RXER hold RXCLK pulse width high RXCLK pulse width low
Min 10 10 35% 35%
Max -- -- 65% 65%
Unit ns ns RXCLK period RXCLK period
M3
RXCLK (input)
M4
RXD[3:0] (inputs) RXDV RXER
M1 M2
Figure 18-24. MII Receive Signal Timing Diagram
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 523
Appendix A Electrical Characteristics
A.13.1.2
MII Transmit Signal Timing (TXD[3:0], TXEN, TXER, TXCLK)
Table A-15. MII Transmit Signal Timing
Num M5 M6 M7 M8 Characteristic TXCLK rise to TXD[3:0], TXEN, TXER invalid TXCLK rise to TXD[3:0], TXEN, TXER valid TXCLK pulse width high TXCLK pulse width low Min 0 -- 35% 35% Max -- 25 65% 65% Unit ns ns TXCLK period TXCLK period
M7
TXCLK (input)
M5 M8
TXD[3:0] (outputs) TXEN TXER
M6 Figure A-2. MII Transmit Signal Timing Diagram
A.13.1.3
MII Asynchronous Inputs Signal Timing (CRS, COL)
Table A-16. MII Transmit Signal Timing
Num M9
Characteristic CRS, COL minimum pulse width
Min 1.5
Max --
Unit TXCLK period
MC9S12NE64 Data Sheet, Rev. 1.1 524 Freescale Semiconductor
EMAC Electrical Characteristics
CRS, COL
M9
Figure A-3. MII Asynchronous Inputs Timing Diagram
A.13.1.4
MII Management Timing (MDIO, MDC)
Table A-17. MII Management Signal Timing
Num M10 M11 M12 M13 M14 M15
Characteristic MDC rise to MDIO (output) invalid MDC rise to MDIO (output) valid MDIO (input) setup to MDC rise MDC rise to MDIO (input) hold MDC pulse width high MDC pulse width low
Min 10 -- 100 0 40% 40%
Max -- 390 -- -- 60% 60%
Unit ns ns ns ns MDC period MDC period
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 525
Appendix A Electrical Characteristics
M14
M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
Figure A-4. MII Serial Management Channel Timing Diagram
MC9S12NE64 Data Sheet, Rev. 1.1 526 Freescale Semiconductor
EPHY Electrical Characteristics
A.14
EPHY Electrical Characteristics
NOTE The electrical characteristics given in the EPHY section are preliminary and should be used as a guide only. Values cannot be guaranteed by Freescale Semiconductor and are subject to change without notice.
Table A-18. 10BASE-T SQE (Heartbeat) Timing Parameters
Num 1 2
C D D
Parameter COL (SQE) delay after TXEN off COL (SQE) pulse duration
Sym t1 t2
Min
Typ 1.0 1.0
Max
Units s s
Typical values are at 25C. 1 BT = Bit Time = 100 ns
TXC
TXEN
t1
t2
COL
Figure A-5. 10BASE-T SQE (Heartbeat) Timing
A.14.1
10BASE-T Jab and Unjab Timing
Table A-19. 10BASE-T Jab and Unjab Timing Parameters
Num 1 2
C D D
Parameter Maximum Transmit time Unjab time
Sym t1 t2
Min
Typ 98 525
Max
Units ms ms
Typical values are at 25C. 1 BT = Bit Time = 100 ns
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 527
Appendix A Electrical Characteristics
TXEN
t1
TXD
COL
t2
Figure A-6. 10BASE-T SQE (Heartbeat) Timing
A.14.2
A.14.2.1
Auto Negotiation
MII - 100BASE-TX Transmit Timing Parameters
Table A-20. MII - Auto Negotiation and Fast Link Pulse Timing Parameters
Num 1 2 3 4 5 6
C D D D D D D
Parameter Clock/data pulse width Clock pulse to clock pulse Clock pulse to data pulse (data = 1) Pulses in a burst FLP burst width FLP burst to FLP burst
Sym t1 t2 t3 t4 t5 t6
Min
Typ 100
Max
Units ns s s # ms ms
111 55.5 17
125 62.5 2
139 69.5 33
8
16
24
Typical values are at 25C. 1 BT = Bit Time = 100 ns These parameters are the minimum and maximum times as specified in section 24.6 of the IEEE 802.3u Standard
t2 t3 t1 t1
TX+
Clock Pulse
Data Pulse
Clock Pulse
Figure A-7. Auto-Negotiation and Fast Link Pulse Timing
MC9S12NE64 Data Sheet, Rev. 1.1 528 Freescale Semiconductor
EPHY Electrical Characteristics
A.14.2.2
MII -- 10BASE-T Receive Timing
Table A-21. Auto-Negotiation and Fast Link Pulse Timing
Num 1 2 3 4 5 6 7 8
C D D D D D D D D
Parameter Transmit FLNP width Receive FLNP width Clock/data pulse width Clock FLNP to clock FLNP Clock FLNP to data FLNP (data = 1) Pulses in a burst FLNP burst width FLNP burst to FLNP burst
Sym
Min 1.25 1
Typ 1.5 1.5 100 125 62.5 2
Max 1.75 2 139 69.5 33
Units s s ns s s # ms ms
t1 t2 t3 t4 t5 t6 8 111 55.5 17
16
24
Typical values are at 25C. 1 BT = Bit Time = 100 ns
FLP BURST FLP BURST
TX+
t5 t6
Figure A-8. Fast Link Pulse Timing
t2 t3 t1 t1
TX+
Clock Pulse
Data Pulse
Clock Pulse
Figure A-9. Auto-Negotiation Pulse Timing
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 529
Appendix A Electrical Characteristics
FLNP Burst
FLNP Burst
TX+
t5 t6
Figure A-10. Fast Link Pulse Timing
Table A-22. 10BASE-T Transceiver Characteristics
Num 1 C D Parameter Peak differential output voltage Transmit timing jitter Receive dc input impedance Receive differential squelch level Sym VOP Min 2.2 Typ 2.5 Max 2.8 Units V Test Conditions With specified transformer and line replaced by 100 (1%) load Using line model specified in the IEEE 802.3 0.0 < Vin < 3.3 V 3.3 MHz sine wave input
2 3 4
D D D
-- Zin Vsquelch
0 -- 300
2 10 400
11 -- 585
ns k mV
Table A-23. 100BASE-TX Transceiver Characteristics
Num 1 C D Parameter Transmit Peak Differential Output Voltage Transmit Signal Amplitude Symmetry Transmit Rise/Fall Time Sym VOP Min 0.95 Typ 1.00 Max 1.05 Units V Test Conditions With specified transformer and line replaced by 100 ( 1%) load With specified transformer and line replaced by 100  (1%) load With specified transformer and line replaced by 100  (1%) load See IEEE 802.3 for details
2
D
Vsym
98
100
102
%
3
D
trf
3
4
5
ns
4 5 6 7 8
D D D D D
Transmit Rise/Fall Time Symmetry Transmit Overshoot/UnderShoot Transmit Jitter Receive Common Mode Voltage Receiver Maximum Input Voltage
trfs Vosh -- Vcm Vmax
-0.5 -- 0 -- --
0 2.5 .6 1.6 --
+0.5 5 1.4 -- 4.7
ns % ns V V
VDDRX = 2.5 V VDDRX = 2.5 V. Internal circuits protected by divider in shutdown
MC9S12NE64 Data Sheet, Rev. 1.1 530 Freescale Semiconductor
EPHY Electrical Characteristics
Table A-24. EPHY Operating Conditions
Num 1 2 3 4 5 6
1
Parameter Crystal 1 Bus clock in single chip mode -- 10 Mbps operation Bus clock in external mode -- 10 Mbps operation Bus clock in single chip mode -- 100 Mbps operation Bus clock in external mode -- 100 Mbps Bias resistor
Min 25 2.5 2.5 25
Typ -- -- -- -- 12.4, 1%
Max 25 25 fo 25
Units MHz MHz MHz MHz k
Not available
Crystal tolerance must conform to IEEE requirements.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 531
Appendix A Electrical Characteristics
A.15
A.15.1
FLASH NVM Electrical Characteristics
NVM timing
The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency fNVMOSC is required for performing program or erase operations. The NVM modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. Programming or erasing the NVM modules at a lower frequency will not result in a full program or erase transition. The FLASH program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV register. The frequency of this clock must be set within the limits specified as fNVMOP. The minimum program and erase times shown in Table A-25 are calculated for maximum fNVMOP and maximum fbus. The maximum times are calculated for minimum fNVMOP and a fbus of 2 MHz.
A.15.1.1
Single Word Programming
The programming time for single word programming is dependent on the bus frequency as a well as on the frequency fNVMOP and can be calculated according to the following formula.
1 1 t swpgm = 9  --------------------- + 25  ---------f NVMOP f bus
A.15.1.2 Burst Programming
FLASH programming where up to 32 words in a row can be programmed consecutively using burst programming by keeping the command pipeline filled. The time to program a consecutive word can be calculated as:
1 1 t bwpgm = 4  --------------------- + 9  ---------f NVMOP f bus
The time to program a whole row is:
t brpgm = t swpgm + 31  t bwpgm
Burst programming is more than two times faster than single word programming.
A.15.1.3
Sector Erase
Erasing a 512 byte FLASH sector takes:
1 t era  4000  --------------------f NVMOP
The setup times can be ignored for this operation.
MC9S12NE64 Data Sheet, Rev. 1.1 532 Freescale Semiconductor
FLASH NVM Electrical Characteristics
A.15.1.4
Mass Erase
Erasing a NVM block takes:
1 t mass  20000  --------------------f NVMOP
The setup times can be ignored for this operation.
Table A-25. NVM Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6
C
D D D P D D P P D
Rating
External oscillator clock Bus frequency for programming or erase operations Operating frequency Single Word programming time FLASH burst programming consecutive word FLASH burst programming time for 32 words Sector erase time Mass erase time Blank check time FLASH per block
Symbol
fNVMOSC fNVMBUS fNVMOP tswpgm tbwpgm tbrpgm tera tmass t check
Min
0.5 1 150 46 2 20.42 678.42 20 4 1004 11 5
Typ
Max
50 1
Unit
MHz MHz
200 74.5 3 313 1035.53 26.73 1333 32778 6
kHz s s s ms ms tcyc
Restrictions for oscillator in crystal mode apply! Minimum programming times are achieved under maximum NVM operating frequency f NVMOP and maximum bus frequency fbus. Maximum erase and programming times are achieved under particular combinations of f NVMOP and bus frequency f bus. Minimum Erase times are achieved under maximum NVM operating frequency f NVMOP. Minimum time, if first word in the array is not blank Maximum time to complete check on an erased block.
A.15.2
NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase cycling are specified at < 2 ppm defects over lifetime at the operating conditions noted. A program/erase cycle is specified as two transitions of the cell value from erased  programmed  erased, 1  0  1.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 533
Appendix A Electrical Characteristics
NOTE All values shown in Table A-26 are target values and subject to further extensive characterization.
Table A-26. NVM Reliability Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num
1 2 3
C
C C C
Rating
Data retention at an average junction temperature of TJavg = 85C Data retention at a junction temperature of TJ = 140C FLASH number of program/erase cycles
Symbol
tNVMRET tNVMRET nFLPE
Min
15 10 10,000
Typ
Max
Unit
Years Years Cycles
MC9S12NE64 Data Sheet, Rev. 1.1 534 Freescale Semiconductor
SPI Electrical Characteristics
A.16
SPI Electrical Characteristics
This section provides electrical parametrics and ratings for the SPI. In Table A-27 the measurement conditions are listed.
Table A-27. Measurement Conditions Description
Drive mode Load capacitance CLOAD, on all outputs Thresholds for delay measurement points
Value
full drive mode 50 (20% / 80%) VDDX
Unit
-- pF V
A.16.1
Master Mode
In Figure A-11 the timing diagram for master mode with transmission format CPHA=0 is depicted.
SS1 (OUTPUT) 2 SCK (CPOL = 0) (OUTPUT) SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 10 MOSI (OUTPUT)
1.if configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
1 4 4
12
13
3
12
13
6 MSB IN2 BIT 6 . . . 1 9 MSB OUT2 BIT 6 . . . 1 LSB OUT LSB IN 11
Figure A-11. SPI Master Timing (CPHA=0)
In Figure A-12 the timing diagram for master mode with transmission format CPHA=1 is depicted.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 535
Appendix A Electrical Characteristics
SS1 (OUTPUT) 1 2 SCK (CPOL = 0) (OUTPUT) 4 SCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA
1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
13
3
4
12
13
6 MSB IN2 BIT 6 . . . 1 11 LSB IN
MASTER MSB OUT2
BIT 6 . . . 1
MASTER LSB OUT
PORT DATA
Figure A-12. SPI Master Timing (CPHA=1)
In Table A-28 the timing characteristics for master mode are listed.
Table A-28. SPI Master Mode Timing Characteristics Num
1 1 2 3 4 5 6 9 10 11 12 13
C
P P D D D D D D D D D D
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Data Valid after SCK Edge Data Valid after SS fall (CPHA=0) Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi tvsck tvss tho trfi trfo
Min
1/2048 2 -- -- -- 8 8 -- -- 20 -- --
Typ
-- -- 1/2 1/2 1/2 -- -- -- -- -- -- --
Max
1/2 2048 -- -- -- -- -- 30 15 -- 8 8
Unit
fbus tbus tsck tsck tsck ns ns ns ns ns ns ns
A.16.2
Slave Mode
In Figure A-13 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
MC9S12NE64 Data Sheet, Rev. 1.1 536 Freescale Semiconductor
SPI Electrical Characteristics
SS (INPUT) 1 SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 10 7 MISO (OUTPUT) see note 5 MOSI (INPUT)
NOTE: Not defined!
12
13
3
4
4
12
13 8
9 SLAVE MSB 6 MSB IN BIT 6 . . . 1 BIT 6 . . . 1
11
11 SEE NOTE
SLAVE LSB OUT
LSB IN
Figure A-13. SPI Slave Timing (CPHA = 0)
In Figure A-14 the timing diagram for slave mode with transmission format CPHA = 1 is depicted.
SS (INPUT) 1 2 SCK (CPOL = 0) (INPUT) 4 SCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) see note 7 MOSI (INPUT)
NOTE: Not defined!
3 12 13
4
12
13
11 MSB OUT 6 BIT 6 . . . 1 SLAVE LSB OUT
8
SLAVE 5
MSB IN
BIT 6 . . . 1
LSB IN
Figure A-14. SPI Slave Timing (CPHA = 1)
In Table A-29 the timing characteristics for slave mode are listed.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 537
Appendix A Electrical Characteristics
Table A-29. SPI Slave Mode Timing Characteristics Num
1 1 2 3 4 5 6 7 8 9 10 11 12 13
1t bus
C
P P D D D D D D D D D D D D
Characteristic
SCK Frequency SCK Period Enable Lead Time Enable Lag Time Clock (SCK) High or Low Time Data Setup Time (Inputs) Data Hold Time (Inputs) Slave Access Time (time to data active) Slave MISO Disable Time Data Valid after SCK Edge Data Valid after SS fall Data Hold Time (Outputs) Rise and Fall Time Inputs Rise and Fall Time Outputs
Symbol
fsck tsck tlead tlag twsck tsu thi ta tdis tvsck tvss tho trfi trfo
Min
DC 4 4 4 4 8 8 -- -- -- -- 20 -- --
Typ
-- -- -- -- -- -- -- -- -- -- -- -- -- --
Max
1/4  -- -- -- -- -- 20 22 30 + tbus -- 8 8
1
Unit
fbus tbus tbus tbus tbus ns ns
ns
ns
ns ns ns ns ns
30 + tbus 1
added due to internal synchronization delay
MC9S12NE64 Data Sheet, Rev. 1.1 538 Freescale Semiconductor
Voltage Regulator Operating Characteristics
A.17
Voltage Regulator Operating Characteristics
Table A-30. VREG_PHY - Operating Conditions
This section describes the characteristics of the on-chip voltage regulator (VREG_PHY).
Num
1 2
C
P P
Characteristic
Input Voltages Regulator Current Reduced Power Mode Shutdown Mode Output Voltage Core Full Performance Mode Reduced Power Mode Shutdown Mode Output Voltage PLL Full Performance Mode Reduced Power Mode 2 Shutdown Mode Low Voltage Reset 4 Assert Level Deassert Level Power-on Reset 5 Assert Level Deassert Level
Symbol
VVDDR,A,X1,X2 IREG
Min
3.135 -- --
Typical
-- 20 12 2.5 2.5
1
Max
3.465 50 40 2.625 2.75 -- 2.625 2.75 --
Unit
V A A V V V V V V
3
P
VDD
2.375 1.6 -- 2.375 1.6 --
4
P
VDDPLL
2.5 2.5
3
5
P
VLVRA VLVRD VPORA VPORD
2.25 --
-- --
-- 2.55
V V
7
C
0.97 --
-----
-- 2.05
V V
High Impedance Output Current IDDPLL = 3 mA (Pierce Oscillator) 3 High Impedance Output 4 Monitors V , active only in Full Performance Mode. V DD LVRA and VPORD must overlap 5 Monitors V . Active in all modes. DD
2
1
The electrical characteristics given in this section are preliminary and should be used as a guide only. Values in this section cannot be guaranteed by Freescale Semiconductor and are subject to change without notice.
A.17.1
MCU Power-Up and LVR Graphical Explanation
Voltage regulator sub modules POR (power-on reset) and LVR (low-voltage reset) handle chip power-up or drops of the supply voltage. Their function is described in Figure A-15.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 539
Appendix A Electrical Characteristics
V
VDD
VLVRD VLVRA VPORD
t
POR
LVR
Figure A-15. Voltage Regulator -- MCU Power-Up And Voltage Drops (Not Scaled)
A.17.2
A.17.2.1
Output Loads
Resistive Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external DC loads.
A.17.2.2
Capacitive Loads
The capacitive loads are specified in Table A-31. Ceramic capacitors with X7R dielectricum are required.
Table A-31. Voltage Regulator -- Capacitive Loads Num
1 2 2 2 2
Characteristic
VDD external capacitive load PHY_VDDTX external capacitive load PHY_VDDRX external capacitive load PHY_VDDA external capacitive load VDDPLL external capacitive load
Symbol
CDDext CDDPLLext CDDPLLext CDDPLLext CDDPLLext
Min
200 90 90 90 90
Typical
440 220 220 220 220
Max
12000 5000 5000 5000 5000
Unit
nF nF nF nF nF
MC9S12NE64 Data Sheet, Rev. 1.1 540 Freescale Semiconductor
External Bus Timing
A.18
External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure 18-25 with the actual timing values shown on table Table A-32. All major bus signals are included in the diagram. Although both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. The expanded bus timings are highly dependent on the load conditions. The timing parameters shown assume a balanced load across all outputs.
1, 2 3 ECLK PE4 5 9 Addr/Data (read) PA, PB data 6 15 addr 7 12 Addr/Data (write) PA, PB data addr 8 14 data 13 16 10 data 11 4
17 R/W PE2
18
19
20 LSTRB PE3
21
22
23 NOACC PE7
24
25
26 PIPO0 PIPO1, PE6,5
27
28
29
Figure 18-25. General External Bus Timing
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 541
Appendix A Electrical Characteristics
Table A-32. Expanded Bus Timing Characteristics (3.3 V Range)
Conditions are VDDX = 3.3 V 5%, Junction Temperature -40C to +125C, CLOAD = 50 pF Num 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
1Affected
C P P D D D D D D D D D D D D D D D D D D D D D D D D D D D
Rating Frequency of operation (E-clock) Cycle time Pulse width, E low Pulse width, E high 1 Address delay time Address valid time to E rise (PWEL-tAD) Muxed address hold time Address hold to data valid Data hold to address Read data setup time Read data hold time Write data delay time Write data hold time Write data setup time1 (PWEH-tDDW) Address access time1 E high access time1 (PWEH-tDSR) Read/write delay time Read/write valid time to E rise (PWEL-tRWD) Read/write hold time Low strobe delay time Low strobe valid time to E rise (PWEL-tLSD) Low strobe hold time NOACC strobe delay time NOACC valid time to E rise (PWEL-tLSD) NOACC hold time IPIPO[1:0] delay time IPIPO[1:0] valid time to E rise (PWEL-tP0D) IPIPO[1:0] delay time1 IPIPO[1:0] valid time to E fall
Symbol fo tcyc PWEL PWEH tAD tAV tMAH tAHDS tDHA tDSR tDHR tDDW tDHW tDSW tACCA tACCE tRWD tRWV tRWH tLSD tLSV tLSH tNOD tNOV tNOH tP0D tP0V tP1D tP1V
Min 0 62.5 30 30
Typ
Max 16.0
Unit MHz ns ns ns
16 16 2 7 2 15 0 15 2 15 29 15 14 16 2 14 16 2 14 16 2 2 16 2 11 25 14
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
by clock stretch: add N x tcyc where N=0,1,2 or 3, depending on the number of clock stretches.
MC9S12NE64 Data Sheet, Rev. 1.1 542 Freescale Semiconductor
Introduction
Appendix B Schematic and PCB Layout Design Recommendations
B.1 Introduction
This sections provides recommendations for schematic and PCB layout design for implementing an Ethernet interface with the MC9S12NE64 microcontroller unit (MCU).
B.1.1
Schematic Designing with the MC9S12NE64 and Adding an Ethernet Interface
Figure B-1 is a schematic of a MC9S12NE64 80-pin package minimum system implementation configured in normal-chip mode and utilizing the internal voltage regulator. This configuration is the recommended implementation for the MC9S12NE64. The schematic provides a reference for the following MC9S12NE64 design items. * Operation mode * Clocks * Power * Ethernet, high-speed LAN magnetics isolation module, and RJ45 Ethernet connector * EPHY status indicators * Background debug connector (J1) To configure the MC9S12NE64 in normal single-chip mode, the MODC, MODB, and MODA pins should be configured as documented in the device overview chapter of this book.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 543
C1 0.22
3.3V
63
64
65
62 PAD1/ AN1
66
68
76
75
77
80
U1
VSSA
VSS1
VRL
VDDA
VDD1
VRH
PAD7/ AN7
PAD6/ AN6
PAD5/ AN5
PAD4/ AN4
PAD3/ AN3
PAD2/ AN2
PT5/ TIM_ IOC5
PT6/ TIM_ IOC6
PJ6/ KWJ6/ IIC_SDA
PJ7/ KWJ7/ IIC_ SCL
PT4/ TIM_ IOC4
PT7/ TIM_ IOC7
PAD0/ AN0
61
67
69
70
71
74
73
72
78
79
3.3V 3.3V
1 2
3 4 5
6 7 8 9
MII_TXER/KWH6/PH6 MII_TXEN/KWH5/PH5 MII_TXCLK/KWH4/PH4 MII_TXD3/KWH3/PH3 MII_TXD2/KWH2/PH2 MII_TXD1/KWH1/PH1 MII_TXD0/KWH0/PH0 MII_MDC/KWJ0/PJ0 MII_MDIO/KWJ1/PJ1 VDDX1 VSSX1 MII_CRS/KWJ2/PJ2 MII_COL/KWJ3/PJ3 MII_RXD0/KWG0/PG0 MII_RXD1/KWG1/PG1 MII_RXD2/KWG2/PG2 MII_RXD3/KWG3/PG3 MII_RXCLK/KWG4/PG4 MII_RXDV/KWG5/PG5
PL0/ACTLED PL0/ACTLED PL1/LNKLED PL1/LNKLED VDDR VDDR PL2/SPDLED PL2/SPDLED PHY_VSSRX PHY_VSSRX PHY_VDDRX PHY_VDDRX PHY_RXN PHY_RXN PHY_RXP PHY_RXP PHY_VSSTX PHY_VSSTX
60 60
PL0/ACTLED PL0/ACTLED
59 59
C2 C2 0.01 0.01
TRANSFORMER //RJ-45 CONNECTOR TRANSFORMER RJ-45 CONNECTOR
PL1/LNKLED
3.3V 3.3V
PL2/SPDLED PL2/SPDLED
58 58 57 57
56 56
C3 C3 0.22 0.22
R1 R1 49.9 49.9
R2 R2 49.9 49.9
T1 T1
6 6
MCU SIDE MCU SIDE
RR-
CABLE SIDE CABLE SIDE
J6 J6 J7 J7 J8 J8 J3 J3 6 6 7 7 8 8 3 3
55 55
54 54
5 5
4 4
75 OHMS 75 OHMS
CT CT R+ R+
53 53
52 52
RJ-45 RJ-45
3 3
TT75 OHMS 75 OHMS
3.3V
10 11
12 13
MC9S12NE64
PHY_TXN PHY_TXN PHY_TXP PHY_TXP PHY_VDDTX PHY_VDDTX PHY_VDDA PHY_VDDA PHY_VSSA PHY_VSSA PHY_RBIAS PHY_RBIAS VDD2 VDD2 VSS2 VSS2 PL3/DUPLED PL3/DUPLED PL4/COLLED PL4/COLLED
51 51
50 50 49 49 48 48
C4 C4 0.22 0.22
2 2
CT CT T+ T+ ..
1000 pF 1000 pF 2kV 2kV
1 1
J2 J2 J4 J4 J5 J5 J1 J1
2 2 4 4 5 5 1 1
C5
0.22
R3 R3 49.9 49.9
R4 R4 49.9 49.9
8 8
14
15 16 17
18 19 20
47 47 46 46 45 45
R5 RBIAS C6 0.22
EARTH/CHASSIS EARTH/CHASSIS
44 44 43 43
PL3/DUPLED PL3/DUPLED
42 42 41 41
PL4/COLLED PL4/COLLED
OPTIONAL STATUS LED's OPTIONAL STATUS LED's
3.3V 3.3V
3.3V 3.3V
SCI0_ RXD/ PS0
SCI1_ RXD/ PS2
SCI1_ TXD/ PS3
SPI_ MISO/ PS4
SCI0_ TXD/ PS1
SPI_ MOSI/ PS5
MII_RXER/KWG6/PG6
BKGD/MODC BKGD/MODC
SPI_ SCK/ PS6
R13 R13
LED1 LED1
SPI_SS/ PS7
XIRQ/ PE0
ECLK/PE4
RESET
VDDX2
VSSX2
IRQ/ PE1
VDDPLL
VSSPLL
10k 10k
R6 R6 220 220
R14 R14 10k 10k
PL1/LNKLED PL1/LNKLED
EXTAL
TEST
XTAL
XFC
LNK_LED LNK_LED
LED2 LED2
J1
1 3 5
12 34 56
2 4 6
3.3V 3.3V
34 34
35 35
36 36
37
38 38
39 39
21 21
31 31
22 22
23 23
24 24
25 25
26 26
27 27
28 28
29
30 30
32
33 33
40 40
*RESET *RESET
R7 R7 220 220
PL2/SPDLED PL2/SPDLED
SPD_LED SPD_LED
BACKGROUND DEBUG
3.3V
*RESET *RESET
LED3 LED3
PL3/DUPLED PL3/DUPLED
R8 R8 220 220
DUP_LED DUP_LED 25 MHz Y1
PL0/ACTLED PL0/ACTLED
R10
ACT_LED ACT_LED LED4 LED4
C7 0.22
R9 R9 220 220
C10
470 pF
10M
C11 4700 pF
R11 2.2k
LED5 LED5
15 pF C8
15 pF C9 15 pF C9
R12 R12 220 220
PL4/COLLED PL4/COLLED
COL_LED COL_LED
Introduction
B.1.2
Power Supply Notes
A 3.3-V power supply is required. This power supply shall be compatible with Table A-7. Supply Current Characteristics.
B.1.3
Clocking Notes
For basic operation of the MC9S12NE64, a 25-MHz crystal is required to provide the clock input to the integrated PHY. The crystal must connect to the MC9S12NE64 in a Pierce configuration by the XTAL and EXTAL pins as shown in Figure B-1. In addition to providing a 25-MHz crystal input, to operate at 100 Mbps, the internal bus clock must be configured as shown in the EPHY electrical characteristics.
B.1.4
EPHY Notes
Figure B-2 provides a close-up view of the EPHY pin connections to a high-speed LAN magnetics isolation module and RJ45 Ethernet connector.
Figure B-2. Ethernet Interface Circuitry
B.1.5
EPHY LED Indicator Notes
The EPHY can be configuring by software to drive indicator pins (PTL[5:0]) automatically by setting the LEDEN bit of the EPHY EPHYCTL0 register. When LEDEN = 1, PTL[5:0] pins are dedicated to the EPHY.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 545
Appendix B Schematic and PCB Layout Design Recommendations
B.2
PCB Design Recommendation
The section provides recommendations for general HCS12 PCB design and recommendations for PCB design with Ethernet.
B.2.1
General PCB Design Recommendations
The PCB layout must be designed to ensure proper operation of the voltage regulator and the MCU. The following recommendations are provided to ensure a robust PCB design: * Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins (C1 - C6). * Central point of the ground star should be the VSSX pin. * Use low ohmic low inductance connections between VSS1, VSS2 and VSSX. * VSSPLL must be directly connected to VSSX. * Keep traces of VSSPLL, EXTAL and XTAL as short as possible and occupied board area for C7,C8, C11 and Q1 as small as possible. * Do not place other signals or supplies underneath area occupied by C7, C8, C10 and Q1 and the connection area to the MCU. * Central power input should be fed in at the VDDA/VSSA pins.
B.2.2
Ethernet PCB Design Recommendations
When designing a PCB that uses the MC9S12NE64 Ethernet module, several design considerations must be made to ensure that Ethernet operation conforms to the IEEE 802.3 physical interface specification. These Ethernet PCB design recommendations include: * The distance between the magnetic module and the RJ-45 jack is the most critical and must always be as short as possible (less than one inch). * Never use 90 traces. Use 45 angles or radius curves in traces. * Trace widths of 0.010" are recommended. Wider is better. Trace widths should not vary. * Route differential Tx and Rx pairs near together (max 0.010" separation with 0.010" traces). * Trace lengths must always be as short as possible (must be less than one inch). * Make trace lengths as equal as possible. * Keep TX and RX differential pairs routes separated (at least 0.020" separation). Better to separate with a ground plane. * Avoid routing Tx and Rx traces over or under a plane. Areas under the Tx and Rx traces should be open. * Use precision components in the line termination circuitry with 1% tolerance. * Ensure that the power supply is rated for a load of 300 mA minimum. * Avoid vias and layer changes.
MC9S12NE64 Data Sheet, Rev. 1.1 546 Freescale Semiconductor
PCB Design Recommendation
*
*
All termination resistors should be near to the driving source. The MCU is the driving source for PHY_TXP and PHY_TXN pins. The high-speed LAN magnetics isolation module is the driving source for PHY_RXP and PHY_RXN pins. 4-layer PCBs recommended to provide better heat dissipation
B.2.2.1
High-Speed LAN Magnetics Isolation Module Requirements
The MC9S12NE64 requires a 1:1 ratio for the high-speed LAN magnetics isolation module for both the receive and the transmit signals. Because the MC9S12NE64 does not implement Auto-MDIX, an Auto-MDIX capable high-speed LAN magnetics isolation module is not required. A high-speed LAN magnetics isolation module with improved return loss characteristics is recommended to avoid Ethernet return loss issues.
B.2.2.2
80-Pin Package Exposed Flag
The 80-pin TQFP-EP package has an exposed flag for heat dissipation and requires special PCB layout to accommodate the flag. There are two ways to accommodate the flag: * Have a hatched pattern in the solder mask * Use small copper areas under the flag The requirement is to have about 50% of the flag soldered to the PC board.
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 547
Appendix B Schematic and PCB Layout Design Recommendations
MC9S12NE64 Data Sheet, Rev. 1.1 548 Freescale Semiconductor
112-Pin LQFP Package
Appendix C Package Information
C.1
PIN 1 IDENT 1
112-Pin LQFP Package
4X 112
0.20 T L-M N
4X 28 TIPS 85 84
0.20 T L-M N
J1 J1 C L
4X
P
VIEW Y
108X
G
X X=L, M OR N
VIEW Y B L M B1 V1 V
J
AA
28
57
F D 0.13
M
BASE METAL
29
56
T L-M N
N A1 S1 A S
ROTATED 90  COUNTERCLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DATUMS L, M AND N TO BE DETERMINED AT SEATING PLANE, DATUM T. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B INCLUDE MOLD MISMATCH. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46. MILLIMETERS MIN MAX 20.000 BSC 10.000 BSC 20.000 BSC 10.000 BSC --1.600 0.050 0.150 1.350 1.450 0.270 0.370 0.450 0.750 0.270 0.330 0.650 BSC 0.090 0.170 0.500 REF 0.325 BSC 0.100 0.200 0.100 0.200 22.000 BSC 11.000 BSC 22.000 BSC 11.000 BSC 0.250 REF 1.000 REF 0.090 0.160 8 0 7 3 13  11  11  13 
SECTION J1-J1
C2 C 0.050 2
VIEW AB 0.10 T
112X
SEATING PLANE
3 T 
R
R2 0.25
GAGE PLANE
R
R1
C1 (Y) (Z) VIEW AB
(K) E
1
DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA  1 2 3
Figure C-1. 112-Pin LQFP Mechanical Drawing (Case No. 987-01)
MC9S12NE64 Data Sheet, Rev. 1.1 Freescale Semiconductor 549
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FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The ARM POWERED logo is a registered trademark of ARM Limited. ARM7TDMI-S is a trademark of ARM Limited. Java and all other Java-based marks are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. The Bluetooth trademarks are owned by their proprietor and used by Freescale Semiconductor, Inc. under license. (c) Freescale Semiconductor, Inc. 2005. All rights reserved. MC9S12NE64V1 Rev. 1.1 06/2006